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git://sourceware.org/git/glibc.git
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Fix misspellings in sysdeps/powerpc -- BZ 25337
All fixes are in comments, so the binaries should be identical before/after this commit, but I can't verify this. Reviewed-by: Rajalakshmi Srinivasaraghavan <rajis@linux.ibm.com>
This commit is contained in:
Paul Pluzhnikov
parent
d13733c166
commit
0b25c28e02
23 changed files with 34 additions and 34 deletions
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@ -18,7 +18,7 @@
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/*
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* Never include sysdeps/powerpc/atomic-machine.h directly.
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* Alway use include/atomic.h which will include either
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* Always use include/atomic.h which will include either
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* sysdeps/powerpc/powerpc32/atomic-machine.h
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* or
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* sysdeps/powerpc/powerpc64/atomic-machine.h
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@ -32,7 +32,7 @@
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/* The current powerpc 32-bit Altivec ABI specifies for SVR4 ABI and EABI
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the vrsave must be at byte 248 & v20 at byte 256. So we must pad this
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correctly on 32 bit. It also insists that vecregs are only gauranteed
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correctly on 32 bit. It also insists that vecregs are only guaranteed
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4 byte alignment so we need to use vperm in the setjmp/longjmp routines.
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We have to version the code because members like int __mask_was_saved
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in the jmp_buf will move as jmp_buf is now larger than 248 bytes. We
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@ -26,10 +26,10 @@
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r5:byte count
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Save return address in r0.
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If destinationn and source are unaligned and copy count is greater than 256
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If destination and source are unaligned and copy count is greater than 256
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then copy 0-3 bytes to make destination aligned.
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If 32 or more bytes to copy we use 32 byte copy loop.
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Finaly we copy 0-31 extra bytes. */
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Finally we copy 0-31 extra bytes. */
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EALIGN (memcpy, 5, 0)
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/* Check if bytes to copy are greater than 256 and if
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@ -27,13 +27,13 @@
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r12:temp return address
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Save return address in r12
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If destinationn is unaligned and count is greater tha 255 bytes
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If destination is unaligned and count is greater than 255 bytes
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set 0-3 bytes to make destination aligned
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If count is greater tha 255 bytes and setting zero to memory
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use dbcz to set memeory when we can
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otherwsie do the follwoing
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If count is greater than 255 bytes and setting zero to memory
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use dbcz to set memory when we can
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otherwise do the following
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If 16 or more words to set we use 16 word copy loop.
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Finaly we set 0-15 extra bytes with string store. */
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Finally we set 0-15 extra bytes with string store. */
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EALIGN (memset, 5, 0)
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rlwinm r11,r4,0,24,31
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@ -27,13 +27,13 @@
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r12:temp return address
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Save return address in r12
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If destinationn is unaligned and count is greater tha 255 bytes
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If destination is unaligned and count is greater than 255 bytes
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set 0-3 bytes to make destination aligned
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If count is greater tha 255 bytes and setting zero to memory
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use dbcz to set memeory when we can
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otherwsie do the follwoing
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If count is greater than 255 bytes and setting zero to memory
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use dbcz to set memory when we can
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otherwise do the following
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If 16 or more words to set we use 16 word copy loop.
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Finaly we set 0-15 extra bytes with string store. */
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Finally we set 0-15 extra bytes with string store. */
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EALIGN (memset, 5, 0)
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rlwinm r11,r4,0,24,31
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@ -1,4 +1,4 @@
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/* Optimized strcasecmp_l implememtation for POWER7.
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/* Optimized strcasecmp_l implementation for POWER7.
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Copyright (C) 2013-2023 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -1,4 +1,4 @@
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/* Optimized strcasecmp_l implememtation for POWER7.
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/* Optimized strcasecmp_l implementation for POWER7.
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Copyright (C) 2013-2023 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -27,7 +27,7 @@ fi
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# We check if compiler supports @notoc generation since there is no
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# gain by enabling it if it will be optimized away by the linker.
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# It also helps linkers that might not optimize it and end up
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# generating stubs with ISA 3.1 instruction even targetting older ISA.
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# generating stubs with ISA 3.1 instruction even targeting older ISA.
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AC_CACHE_CHECK([if the compiler supports @notoc],
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libc_cv_ppc64_notoc, [dnl
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cat > conftest.c <<EOF
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@ -34,7 +34,7 @@
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Redirect func to a function named function ## variant ## reentrant_suffix
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F128_REDIR(function)
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Convience wrapper for F128_REDIR_R where function does not require
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Convenience wrapper for F128_REDIR_R where function does not require
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a suffix argument.
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*/
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@ -68,7 +68,7 @@
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_F128_IFUNC2 (__ ## func ## f128, pfx2 ## func ## f128, r);
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/* GEN_COMPAT_R_e(f)
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Generate a compatability symbol for finite alias of ieee function. */
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Generate a compatibility symbol for finite alias of ieee function. */
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#define GEN_COMPAT_R_e(f, r) \
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libm_alias_finite (__ieee754_ ## f ## f128 ## r, __ ## f ## f128 ## r)
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@ -44,7 +44,7 @@
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#include <float128-ifunc-macros.h>
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/* Declare these now. These prototyes are not included
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/* Declare these now. These prototypes are not included
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in any header. */
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extern __typeof (cosf128) __ieee754_cosf128;
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extern __typeof (asinhf128) __ieee754_asinhf128;
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@ -425,7 +425,7 @@ L(end_unaligned_loop):
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/* Return original DST pointer. */
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blr
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/* Start to memcpy backward implementation: the algorith first check if
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/* Start to memcpy backward implementation: the algorithm first check if
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src and dest have the same alignment and if it does align both to 16
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bytes and copy using VSX instructions.
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If does not, align dest to 16 bytes and use VMX (altivec) instruction
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@ -17,7 +17,7 @@
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<https://www.gnu.org/licenses/>. */
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/* The optimization is achieved here through cmpb instruction.
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8byte aligned strings are processed with double word comparision
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8byte aligned strings are processed with double word comparison
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and unaligned strings are handled effectively with loop unrolling
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technique */
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@ -479,7 +479,7 @@ L(storebyte2):
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rldicl r6, r3, 0, 61 /* Recalculate padding */
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mr r7, r6
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/* src is algined */
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/* src is aligned */
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L(srcaligndstunalign):
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mr r9, r3
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mr r6, r7
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@ -31,7 +31,7 @@ ENTRY_TOCLESS (STRRCHR)
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clrrdi r8,r3,3 /* Align the address to doubleword boundary. */
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cmpdi cr7,r4,0
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ld r12,0(r8) /* Load doubleword from memory. */
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li r9,0 /* used to store last occurence */
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li r9,0 /* used to store last occurrence */
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li r0,0 /* Doubleword with null chars to use
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with cmpb. */
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@ -137,7 +137,7 @@ ENTRY (STRCASESTR, 4)
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beq cr7, L(skipcheck)
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cmpw cr7, r3, r29
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ble cr7, L(firstpos)
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/* Move r3 to the first occurence. */
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/* Move r3 to the first occurrence. */
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L(skipcheck):
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mr r3, r29
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L(firstpos):
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@ -448,7 +448,7 @@ L(loop1):
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beq cr7, L(skipcheck1)
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cmpw cr7, r3, r29
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ble cr7, L(nextpos)
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/* Move r3 to first occurence. */
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/* Move r3 to first occurrence. */
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L(skipcheck1):
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mr r3, r29
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L(nextpos):
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@ -207,7 +207,7 @@ L(check_source2_byte_loop):
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bdnz L(check_source2_byte_loop)
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/* If source2 is unaligned to doubleword, the code needs to check
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on each interation if the unaligned doubleword access will cross
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on each iteration if the unaligned doubleword access will cross
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a 4k page boundary. */
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.align 5
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L(loop_unaligned):
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@ -65,7 +65,7 @@ ENTRY_TOCLESS (STRLEN, 4)
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L(align64):
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/* Proceed to the old (POWER7) implementation, checking two doublewords
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per iteraction. For the first 56 bytes, we will just check for null
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per iteration. For the first 56 bytes, we will just check for null
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characters. After that, we will also check if we are 64-byte aligned
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so we can jump to the vectorized implementation. We will unroll
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these loops to avoid excessive branching. */
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@ -101,7 +101,7 @@ L(align_8b):
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b L(loop_ne_align_1)
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/* If source2 is unaligned to doubleword, the code needs to check
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on each interation if the unaligned doubleword access will cross
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on each iteration if the unaligned doubleword access will cross
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a 4k page boundary. */
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.align 4
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L(loop_ne_align_0):
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@ -144,7 +144,7 @@ L(short_path_2):
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.align 4
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L(short_path_loop):
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/* At this point, the induction variable, r5, as well as the pointers
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to dest and src (r9 and r4, respectivelly) have been updated.
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to dest and src (r9 and r4, respectively) have been updated.
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Note: The registers r7 and r10 are induction variables derived from
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r5. They are used to determine if the total number of writes has
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@ -351,7 +351,7 @@ L(pagecross):
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cmpdi cr7,r9,0
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bne cr7,L(short_path_prepare_2)
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/* No null byte found in the 32 bytes readed and length not reached,
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/* No null byte found in the 32 bytes read and length not reached,
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read source again using unaligned loads and store them. */
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ld r9,0(r4)
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addi r29,r3,16
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@ -166,7 +166,7 @@ L(loop_64B):
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vminub v6,v3,v4
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vminub v7,v5,v6
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vcmpequb. v7,v7,v0 /* Check for null bytes. */
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addi r5,r5,64 /* Add pointer to next iteraction. */
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addi r5,r5,64 /* Add pointer to next iteration. */
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bne cr6,L(found_64B) /* If found null bytes. */
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bdnz L(loop_64B) /* Continue the loop if count > 0. */
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@ -74,7 +74,7 @@ ENTRY_TOCLESS (STRRCHR)
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clrrdi r8,r3,3 /* Align the address to doubleword boundary. */
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cmpdi cr7,r4,0
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ld r12,0(r8) /* Load doubleword from memory. */
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li r9,0 /* Used to store last occurence. */
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li r9,0 /* Used to store last occurrence. */
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li r0,0 /* Doubleword with null chars to use
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with cmpb. */
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@ -20,7 +20,7 @@
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#include <string.h>
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#include <setjmp.h>
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/* Copy r1 adress to a local variable. */
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/* Copy r1 address to a local variable. */
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#define GET_STACK_POINTER(sp) \
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({ \
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asm volatile ("mr %0, 1\n\t" \
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