<sys/platform/x86.h>: Add RAO-INT support

Add RAO-INT support to <sys/platform/x86.h>.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
This commit is contained in:
H.J. Lu 2023-04-05 09:21:33 -07:00
parent fb90dc8513
commit 231bf916ce
5 changed files with 10 additions and 0 deletions

View file

@ -516,6 +516,9 @@ extended state management using XSAVE/XRSTOR.
@item @item
@code{PTWRITE} -- PTWRITE instruction. @code{PTWRITE} -- PTWRITE instruction.
@item
@code{RAO_INT} -- RAO-INT instructions.
@item @item
@code{RDPID} -- RDPID instruction. @code{RDPID} -- RDPID instruction.

View file

@ -288,6 +288,7 @@ enum
= (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int) = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
+ cpuid_register_index_eax * 8 * sizeof (unsigned int)), + cpuid_register_index_eax * 8 * sizeof (unsigned int)),
x86_cpu_RAO_INT = x86_cpu_index_7_ecx_1_eax + 3,
x86_cpu_AVX_VNNI = x86_cpu_index_7_ecx_1_eax + 4, x86_cpu_AVX_VNNI = x86_cpu_index_7_ecx_1_eax + 4,
x86_cpu_AVX512_BF16 = x86_cpu_index_7_ecx_1_eax + 5, x86_cpu_AVX512_BF16 = x86_cpu_index_7_ecx_1_eax + 5,
x86_cpu_FZLRM = x86_cpu_index_7_ecx_1_eax + 10, x86_cpu_FZLRM = x86_cpu_index_7_ecx_1_eax + 10,

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@ -99,6 +99,7 @@ update_active (struct cpu_features *cpu_features)
CPU_FEATURE_SET_ACTIVE (cpu_features, TBM); CPU_FEATURE_SET_ACTIVE (cpu_features, TBM);
CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP); CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD); CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM); CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS); CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS); CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);

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@ -302,6 +302,7 @@ enum
/* CPUID_INDEX_7_ECX_1. */ /* CPUID_INDEX_7_ECX_1. */
/* EAX. */ /* EAX. */
#define bit_cpu_RAO_INT (1u << 3)
#define bit_cpu_AVX_VNNI (1u << 4) #define bit_cpu_AVX_VNNI (1u << 4)
#define bit_cpu_AVX512_BF16 (1u << 5) #define bit_cpu_AVX512_BF16 (1u << 5)
#define bit_cpu_FZLRM (1u << 10) #define bit_cpu_FZLRM (1u << 10)
@ -537,6 +538,7 @@ enum
/* CPUID_INDEX_7_ECX_1. */ /* CPUID_INDEX_7_ECX_1. */
/* EAX. */ /* EAX. */
#define index_cpu_RAO_INT CPUID_INDEX_7_ECX_1
#define index_cpu_AVX_VNNI CPUID_INDEX_7_ECX_1 #define index_cpu_AVX_VNNI CPUID_INDEX_7_ECX_1
#define index_cpu_AVX512_BF16 CPUID_INDEX_7_ECX_1 #define index_cpu_AVX512_BF16 CPUID_INDEX_7_ECX_1
#define index_cpu_FZLRM CPUID_INDEX_7_ECX_1 #define index_cpu_FZLRM CPUID_INDEX_7_ECX_1
@ -772,6 +774,7 @@ enum
/* CPUID_INDEX_7_ECX_1. */ /* CPUID_INDEX_7_ECX_1. */
/* EAX. */ /* EAX. */
#define reg_RAO_INT eax
#define reg_AVX_VNNI eax #define reg_AVX_VNNI eax
#define reg_AVX512_BF16 eax #define reg_AVX512_BF16 eax
#define reg_FZLRM eax #define reg_FZLRM eax

View file

@ -200,6 +200,7 @@ do_test (void)
CHECK_CPU_FEATURE_PRESENT (XFD); CHECK_CPU_FEATURE_PRESENT (XFD);
CHECK_CPU_FEATURE_PRESENT (INVARIANT_TSC); CHECK_CPU_FEATURE_PRESENT (INVARIANT_TSC);
CHECK_CPU_FEATURE_PRESENT (WBNOINVD); CHECK_CPU_FEATURE_PRESENT (WBNOINVD);
CHECK_CPU_FEATURE_PRESENT (RAO_INT);
CHECK_CPU_FEATURE_PRESENT (AVX_VNNI); CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
CHECK_CPU_FEATURE_PRESENT (AVX512_BF16); CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
CHECK_CPU_FEATURE_PRESENT (FZLRM); CHECK_CPU_FEATURE_PRESENT (FZLRM);
@ -365,6 +366,7 @@ do_test (void)
CHECK_CPU_FEATURE_ACTIVE (XFD); CHECK_CPU_FEATURE_ACTIVE (XFD);
CHECK_CPU_FEATURE_ACTIVE (INVARIANT_TSC); CHECK_CPU_FEATURE_ACTIVE (INVARIANT_TSC);
CHECK_CPU_FEATURE_ACTIVE (WBNOINVD); CHECK_CPU_FEATURE_ACTIVE (WBNOINVD);
CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI); CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16); CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
CHECK_CPU_FEATURE_ACTIVE (FZLRM); CHECK_CPU_FEATURE_ACTIVE (FZLRM);