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Fix misspellings -- BZ 25337

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This commit is contained in:
Paul Pluzhnikov 2023-06-19 21:58:33 +00:00
parent 2d88df5411
commit 4290aed051
2 changed files with 2 additions and 2 deletions
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2
sysdeps/x86/cpu-features.c
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@ -579,7 +579,7 @@ intel_get_fam6_microarch (unsigned int model,
else else
-> Skylake-avx512 -> Skylake-avx512
These are all microarchitecturally indentical, so use These are all microarchitecturally identical, so use
Skylake-avx512 for all of them. Skylake-avx512 for all of them.
*/ */
return INTEL_BIGCORE_SKYLAKE_AVX512; return INTEL_BIGCORE_SKYLAKE_AVX512;

2
sysdeps/x86/dl-cacheinfo.h
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@ -745,7 +745,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
/* The default setting for the non_temporal threshold is [1/8, 1/2] of size /* The default setting for the non_temporal threshold is [1/8, 1/2] of size
of the chip's cache (depending on `cachesize_non_temporal_divisor` which of the chip's cache (depending on `cachesize_non_temporal_divisor` which
is microarch specific. The defeault is 1/4). For most Intel and AMD is microarch specific. The default is 1/4). For most Intel and AMD
processors with an initial release date between 2017 and 2023, a thread's processors with an initial release date between 2017 and 2023, a thread's
typical share of the cache is from 18-64MB. Using a reasonable size typical share of the cache is from 18-64MB. Using a reasonable size
fraction of L3 is meant to estimate the point where non-temporal stores fraction of L3 is meant to estimate the point where non-temporal stores