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LoongArch: Ensure sp 16-byte aligned for tlsdesc

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"ADDI sp, sp, 24" and "ADDI sp, sp, SZFCSREG" (SZFCSREG = 4) are
misaligning the stack: the ABI mandates a 16-byte alignment.  Fix it
by changing the first one to "ADDI sp, sp, 32", and reuse the spare 4th
slot for saving fcsr.

Reported-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
This commit is contained in:
Xi Ruoyao 2024-06-13 19:04:05 +08:00 • committed by caiyinyu
parent 868ab8923a
commit 97aa7b7346
2 changed files with 4 additions and 7 deletions
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10
sysdeps/loongarch/dl-tlsdesc.S
View file

@ -100,7 +100,7 @@ _dl_tlsdesc_undefweak:
_dl_tlsdesc_dynamic: _dl_tlsdesc_dynamic:
/* Save just enough registers to support fast path, if we fall /* Save just enough registers to support fast path, if we fall
into slow path we will save additional registers. */ into slow path we will save additional registers. */
ADDI sp, sp, -24 ADDI sp, sp, -32
REG_S t0, sp, 0 REG_S t0, sp, 0
REG_S t1, sp, 8 REG_S t1, sp, 8
REG_S t2, sp, 16 REG_S t2, sp, 16
@ -141,7 +141,7 @@ Hign address dynamic_block1 <----- dtv5 */
REG_L t0, sp, 0 REG_L t0, sp, 0
REG_L t1, sp, 8 REG_L t1, sp, 8
REG_L t2, sp, 16 REG_L t2, sp, 16
ADDI sp, sp, 24 ADDI sp, sp, 32
RET RET
.Lslow: .Lslow:
@ -171,9 +171,8 @@ Hign address dynamic_block1 <----- dtv5 */
/* Save fcsr0 register. /* Save fcsr0 register.
Only one physical fcsr0 register, fcsr1-fcsr3 are aliases Only one physical fcsr0 register, fcsr1-fcsr3 are aliases
of some fields in fcsr0. */ of some fields in fcsr0. */
ADDI sp, sp, -SZFCSREG
movfcsr2gr t0, fcsr0 movfcsr2gr t0, fcsr0
st.w t0, sp, 0 st.w t0, sp, FRAME_SIZE + 24 /* Use the spare slot above t2 */
/* Whether support LASX. */ /* Whether support LASX. */
la.global t0, _rtld_global_ro la.global t0, _rtld_global_ro
@ -406,9 +405,8 @@ Hign address dynamic_block1 <----- dtv5 */
.Lfcsr: .Lfcsr:
/* Restore fcsr0 register. */ /* Restore fcsr0 register. */
ld.w t0, sp, 0 ld.w t0, sp, FRAME_SIZE + 24
movgr2fcsr fcsr0, t0 movgr2fcsr fcsr0, t0
ADDI sp, sp, SZFCSREG
#endif /* #ifndef __loongarch_soft_float */ #endif /* #ifndef __loongarch_soft_float */

1
sysdeps/loongarch/sys/asm.h
View file

@ -25,7 +25,6 @@
/* Macros to handle different pointer/register sizes for 32/64-bit code. */ /* Macros to handle different pointer/register sizes for 32/64-bit code. */
#define SZREG 8 #define SZREG 8
#define SZFREG 8 #define SZFREG 8
#define SZFCSREG 4
#define SZVREG 16 #define SZVREG 16
#define SZXREG 32 #define SZXREG 32
#define REG_L ld.d #define REG_L ld.d