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x86: Fix for cache computation on AMD legacy cpus.
Some legacy AMD CPUs and hypervisors have the _cpuid_ '0x8000_001D' set to Zero, thus resulting in zeroed-out computed cache values. This patch reintroduces the old way of cache computation as a fail-safe option to handle these exceptions. Fixed 'level4_cache_size' value through handle_amd(). Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com> Tested-by: Florian Weimer <fweimer@redhat.com>
This commit is contained in:
Sajan Karumanchi
Prem Mallappa
parent
53850f044f
commit
dcad5c8578
1 changed files with 199 additions and 27 deletions
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@ -315,40 +315,206 @@ handle_amd (int name)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int ecx = 0;
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unsigned int edx;
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unsigned int count = 0x1;
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unsigned int max_cpuid = 0;
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unsigned int fn = 0;
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/* No level 4 cache (yet). */
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if (name > _SC_LEVEL3_CACHE_LINESIZE)
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return 0;
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if (name >= _SC_LEVEL3_CACHE_SIZE)
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count = 0x3;
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else if (name >= _SC_LEVEL2_CACHE_SIZE)
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count = 0x2;
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else if (name >= _SC_LEVEL1_DCACHE_SIZE)
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count = 0x0;
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__cpuid (0x80000000, max_cpuid, ebx, ecx, edx);
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__cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);
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if (max_cpuid >= 0x8000001D)
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/* Use __cpuid__ '0x8000_001D' to compute cache details. */
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{
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unsigned int count = 0x1;
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if (name >= _SC_LEVEL3_CACHE_SIZE)
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count = 0x3;
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else if (name >= _SC_LEVEL2_CACHE_SIZE)
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count = 0x2;
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else if (name >= _SC_LEVEL1_DCACHE_SIZE)
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count = 0x0;
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__cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);
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if (ecx != 0)
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{
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_ASSOC:
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case _SC_LEVEL1_DCACHE_ASSOC:
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case _SC_LEVEL2_CACHE_ASSOC:
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case _SC_LEVEL3_CACHE_ASSOC:
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return ((ebx >> 22) & 0x3ff) + 1;
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case _SC_LEVEL1_ICACHE_LINESIZE:
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case _SC_LEVEL1_DCACHE_LINESIZE:
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case _SC_LEVEL2_CACHE_LINESIZE:
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case _SC_LEVEL3_CACHE_LINESIZE:
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return (ebx & 0xfff) + 1;
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case _SC_LEVEL1_ICACHE_SIZE:
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case _SC_LEVEL1_DCACHE_SIZE:
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case _SC_LEVEL2_CACHE_SIZE:
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case _SC_LEVEL3_CACHE_SIZE:
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return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);
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default:
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__builtin_unreachable ();
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}
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return -1;
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}
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}
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/* Legacy cache computation for CPUs prior to Bulldozer family.
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This is also a fail-safe mechanism for some hypervisors that
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accidentally configure __cpuid__ '0x8000_001D' to Zero. */
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fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
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if (max_cpuid < fn)
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return 0;
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__cpuid (fn, eax, ebx, ecx, edx);
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if (name < _SC_LEVEL1_DCACHE_SIZE)
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{
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name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
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ecx = edx;
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}
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_ASSOC:
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case _SC_LEVEL1_DCACHE_ASSOC:
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case _SC_LEVEL2_CACHE_ASSOC:
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case _SC_LEVEL1_DCACHE_SIZE:
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return (ecx >> 14) & 0x3fc00;
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case _SC_LEVEL1_DCACHE_ASSOC:
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ecx >>= 16;
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if ((ecx & 0xff) == 0xff)
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{
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/* Fully associative. */
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return (ecx << 2) & 0x3fc00;
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}
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return ecx & 0xff;
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case _SC_LEVEL1_DCACHE_LINESIZE:
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return ecx & 0xff;
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case _SC_LEVEL2_CACHE_SIZE:
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return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
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case _SC_LEVEL2_CACHE_ASSOC:
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switch ((ecx >> 12) & 0xf)
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{
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case 0:
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case 1:
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case 2:
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case 4:
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return (ecx >> 12) & 0xf;
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case 6:
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return 8;
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case 8:
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return 16;
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case 10:
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return 32;
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case 11:
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return 48;
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case 12:
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return 64;
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case 13:
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return 96;
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case 14:
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return 128;
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case 15:
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return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
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default:
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return 0;
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}
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case _SC_LEVEL2_CACHE_LINESIZE:
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return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
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case _SC_LEVEL3_CACHE_SIZE:
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{
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long int total_l3_cache = 0, l3_cache_per_thread = 0;
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unsigned int threads = 0;
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const struct cpu_features *cpu_features;
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if ((edx & 0xf000) == 0)
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return 0;
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total_l3_cache = (edx & 0x3ffc0000) << 1;
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cpu_features = __get_cpu_features ();
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/* Figure out the number of logical threads that share L3. */
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if (max_cpuid >= 0x80000008)
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{
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/* Get width of APIC ID. */
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__cpuid (0x80000008, eax, ebx, ecx, edx);
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threads = (ecx & 0xff) + 1;
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}
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if (threads == 0)
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{
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/* If APIC ID width is not available, use logical
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processor count. */
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__cpuid (0x00000001, eax, ebx, ecx, edx);
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if ((edx & (1 << 28)) != 0)
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threads = (ebx >> 16) & 0xff;
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}
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/* Cap usage of highest cache level to the number of
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supported threads. */
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if (threads > 0)
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l3_cache_per_thread = total_l3_cache/threads;
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/* Get shared cache per ccx for Zen architectures. */
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if (cpu_features->basic.family >= 0x17)
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{
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long int l3_cache_per_ccx = 0;
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/* Get number of threads share the L3 cache in CCX. */
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__cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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l3_cache_per_ccx = l3_cache_per_thread * threads_per_ccx;
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return l3_cache_per_ccx;
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}
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else
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{
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return l3_cache_per_thread;
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}
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}
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case _SC_LEVEL3_CACHE_ASSOC:
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return ecx ? ((ebx >> 22) & 0x3ff) + 1 : 0;
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case _SC_LEVEL1_ICACHE_LINESIZE:
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case _SC_LEVEL1_DCACHE_LINESIZE:
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case _SC_LEVEL2_CACHE_LINESIZE:
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switch ((edx >> 12) & 0xf)
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{
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case 0:
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case 1:
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case 2:
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case 4:
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return (edx >> 12) & 0xf;
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case 6:
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return 8;
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case 8:
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return 16;
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case 10:
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return 32;
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case 11:
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return 48;
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case 12:
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return 64;
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case 13:
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return 96;
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case 14:
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return 128;
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case 15:
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return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
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default:
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return 0;
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}
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case _SC_LEVEL3_CACHE_LINESIZE:
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return ecx ? (ebx & 0xfff) + 1 : 0;
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case _SC_LEVEL1_ICACHE_SIZE:
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case _SC_LEVEL1_DCACHE_SIZE:
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case _SC_LEVEL2_CACHE_SIZE:
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case _SC_LEVEL3_CACHE_SIZE:
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return ecx ? (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1): 0;
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return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
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default:
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__builtin_unreachable ();
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}
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@ -703,7 +869,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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shared_per_thread = shared;
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level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE);
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level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE);
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@ -716,13 +881,20 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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level3_cache_size = shared;
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level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC);
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level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE);
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level4_cache_size = handle_amd (_SC_LEVEL4_CACHE_SIZE);
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if (shared <= 0)
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/* No shared L3 cache. All we have is the L2 cache. */
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shared = core;
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{
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/* No shared L3 cache. All we have is the L2 cache. */
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shared = core;
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}
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else if (cpu_features->basic.family < 0x17)
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{
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/* Account for exclusive L2 and L3 caches. */
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shared += core;
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}
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if (shared_per_thread <= 0)
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shared_per_thread = shared;
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shared_per_thread = shared;
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}
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cpu_features->level1_icache_size = level1_icache_size;
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