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[powerpc] __fesetround_inline optimizations

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On POWER9, use more efficient means to update the 2-bit rounding mode
via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions
or one 'mtfsfi' instruction that modifies 4 bits).

Suggested-by: Paul E. Murphy  <murphyp@linux.ibm.com>
Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
This commit is contained in:
Paul A. Clarke 2019-09-19 11:39:44 -05:00
parent 7413c188c7
commit e68b1151f7
2 changed files with 21 additions and 3 deletions
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6
ChangeLog
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@ -1,3 +1,9 @@
2019-09-27 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use
'mffscrn' instruction on POWER9.
(__fesetround_inline_nocheck): Likewise.
2019-09-27 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (FPSCR_EXCEPTIONS_MASK): New.

18
sysdeps/powerpc/fpu/fenv_libc.h
View file

@ -148,7 +148,12 @@ typedef union
static inline int
__fesetround_inline (int round)
{
if ((unsigned int) round < 2)
#ifdef _ARCH_PWR9
__fe_mffscrn (round);
#else
if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
__fe_mffscrn (round);
else if ((unsigned int) round < 2)
{
asm volatile ("mtfsb0 30");
if ((unsigned int) round == 0)
@ -164,7 +169,7 @@ __fesetround_inline (int round)
else
asm volatile ("mtfsb1 31");
}
#endif
return 0;
}
@ -173,7 +178,14 @@ __fesetround_inline (int round)
static inline void
__fesetround_inline_nocheck (const int round)
{
asm volatile ("mtfsfi 7,%0" : : "i" (round));
#ifdef _ARCH_PWR9
__fe_mffscrn (round);
#else
if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
__fe_mffscrn (round);
else
asm volatile ("mtfsfi 7,%0" : : "i" (round));
#endif
}
#define FPSCR_MASK(bit) (1 << (31 - (bit)))