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2f5524cc53
The latest implementations of memcpy are actually faster than the Falkor implementations [1], so remove the falkor/phecda ifuncs for memcpy and the now unused IS_FALKOR/IS_PHECDA defines. [1] https://sourceware.org/pipermail/libc-alpha/2022-December/144227.html Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/* Initialize CPU feature data. AArch64 version.
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This file is part of the GNU C Library.
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Copyright (C) 2017-2023 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _CPU_FEATURES_AARCH64_H
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#define _CPU_FEATURES_AARCH64_H
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#include <stdint.h>
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#include <stdbool.h>
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
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&& MIDR_PARTNUM(midr) == 0x0a1)
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#define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B' \
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&& MIDR_PARTNUM(midr) == 0x516)
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#define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
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&& MIDR_PARTNUM(midr) == 0xaf)
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#define IS_NEOVERSE_N1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
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&& MIDR_PARTNUM(midr) == 0xd0c)
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#define IS_NEOVERSE_N2(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
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&& MIDR_PARTNUM(midr) == 0xd49)
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#define IS_NEOVERSE_V1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
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&& MIDR_PARTNUM(midr) == 0xd40)
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#define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P' \
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&& MIDR_PARTNUM(midr) == 0x000)
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#define IS_KUNPENG920(midr) (MIDR_IMPLEMENTOR(midr) == 'H' \
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&& MIDR_PARTNUM(midr) == 0xd01)
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#define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F' \
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&& MIDR_PARTNUM(midr) == 0x001)
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struct cpu_features
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{
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uint64_t midr_el1;
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unsigned zva_size;
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bool bti;
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/* Currently, the GLIBC memory tagging tunable only defines 8 bits. */
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uint8_t mte_state;
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bool sve;
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bool mops;
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};
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#endif /* _CPU_FEATURES_AARCH64_H */
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