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f42634f824
If the bit is not 0, the operations FRCHG and FSCHG are undefined and cause a trap; qemu now checks for this as well, so we set it to 0 temporarily and restore the old value in getcontext afterwards (setcontext/swapcontext already do so). From the discussion in the bugreport, this can probably be optimised in one place but none of the people involved are SH4 assembly experts, this patch is field-tested, and it’s not a code path run often. The other question, what happens if a signal occurs while the bit is temporarily 0, is also still unsolved, but to fix that a kernel change is most likely needed; this patch changes a certain trap on many CPUs for a hard-to-get trap in a signal handler if a signal is delivered during the few instructions the PR bit is temporarily set to 0, so it’s not a regression for most users. See BZ and https://bugs.launchpad.net/qemu/+bug/1796520 for related discussion, references and review comments. Signed-off-by: mirabilos <tg@debian.org> Reviewed-by: Oleg Endo <olegendo@gcc.gnu.org> Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
220 lines
4.4 KiB
ArmAsm
220 lines
4.4 KiB
ArmAsm
/* Save current context and install the given one.
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Copyright (C) 2005-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include "ucontext_i.h"
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/* int __swapcontext (ucontext_t *ouc, const ucontext_t *uc); */
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.text
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.align 5
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ENTRY(__swapcontext)
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/* Return value of getcontext. R0 is the only register whose
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value is not preserved. */
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mov #0, r0
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mov.l r0, @(oR0,r4)
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mov.l r1, @(oR1,r4)
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mov.l r2, @(oR2,r4)
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mov.l r3, @(oR3,r4)
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mov.l r4, @(oR4,r4)
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mov.l r5, @(oR5,r4)
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mov.l r6, @(oR6,r4)
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mov.l r7, @(oR7,r4)
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mov r4, r0
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add #(oMACL+4), r0
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sts.l macl, @-r0
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sts.l mach, @-r0
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stc.l gbr, @-r0
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/* Save T flag to SR. */
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movt r1
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mov.l r1, @-r0
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sts.l pr, @-r0
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/* The return address of getcontext is the restart pc. */
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sts.l pr, @-r0
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mov.l r15, @-r0
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mov.l r14, @-r0
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mov.l r13, @-r0
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mov.l r12, @-r0
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mov.l r11, @-r0
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mov.l r10, @-r0
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mov.l r9, @-r0
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mov.l r8, @-r0
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#ifdef __SH_FPU_ANY__
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mov r4, r0
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/* We need 2 add instruction because oFPUL+4 >= 127. */
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add #124,r0
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add #(oFPUL+4-124),r0
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sts.l fpul, @-r0
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sts.l fpscr, @-r0
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mov #0, r9
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lds r9, fpscr
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frchg
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fmov.s fr15, @-r0
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fmov.s fr14, @-r0
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fmov.s fr13, @-r0
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fmov.s fr12, @-r0
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fmov.s fr11, @-r0
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fmov.s fr10, @-r0
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fmov.s fr9, @-r0
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fmov.s fr8, @-r0
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fmov.s fr7, @-r0
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fmov.s fr6, @-r0
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fmov.s fr5, @-r0
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fmov.s fr4, @-r0
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fmov.s fr3, @-r0
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fmov.s fr2, @-r0
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fmov.s fr1, @-r0
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fmov.s fr0, @-r0
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frchg
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fmov.s fr15, @-r0
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fmov.s fr14, @-r0
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fmov.s fr13, @-r0
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fmov.s fr12, @-r0
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fmov.s fr11, @-r0
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fmov.s fr10, @-r0
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fmov.s fr9, @-r0
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fmov.s fr8, @-r0
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fmov.s fr7, @-r0
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fmov.s fr6, @-r0
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fmov.s fr5, @-r0
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fmov.s fr4, @-r0
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fmov.s fr3, @-r0
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fmov.s fr2, @-r0
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fmov.s fr1, @-r0
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fmov.s fr0, @-r0
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#endif /* __SH_FPU_ANY__ */
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mov r5, r8
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/* sigprocmask (SIG_SETMASK, &uc->uc_sigmask, &ouc->uc_sigmask). */
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mov #oSIGMASK, r1
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extu.b r1, r1
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add r1, r5
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mov r4, r6
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add r1, r6
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mov #SIG_SETMASK, r4
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mov #+SYS_ify(sigprocmask), r3
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trapa #0x13
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mov r0, r1
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mov #-12, r2
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shad r2, r1
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not r1, r1 // r1=0 means r0 = -1 to -4095
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tst r1, r1 // i.e. error in linux
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bf .Lswapcontext_restore
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.Lsyscall_error:
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SYSCALL_ERROR_HANDLER
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.Lpseudo_end:
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rts
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nop
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.Lswapcontext_restore:
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#ifdef __SH_FPU_ANY__
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mov r8, r0
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add #(oFR0),r0
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fmov.s @r0+, fr0
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fmov.s @r0+, fr1
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fmov.s @r0+, fr2
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fmov.s @r0+, fr3
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fmov.s @r0+, fr4
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fmov.s @r0+, fr5
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fmov.s @r0+, fr6
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fmov.s @r0+, fr7
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fmov.s @r0+, fr8
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fmov.s @r0+, fr9
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fmov.s @r0+, fr10
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fmov.s @r0+, fr11
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fmov.s @r0+, fr12
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fmov.s @r0+, fr13
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fmov.s @r0+, fr14
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fmov.s @r0+, fr15
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frchg
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fmov.s @r0+, fr0
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fmov.s @r0+, fr1
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fmov.s @r0+, fr2
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fmov.s @r0+, fr3
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fmov.s @r0+, fr4
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fmov.s @r0+, fr5
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fmov.s @r0+, fr6
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fmov.s @r0+, fr7
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fmov.s @r0+, fr8
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fmov.s @r0+, fr9
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fmov.s @r0+, fr10
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fmov.s @r0+, fr11
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fmov.s @r0+, fr12
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fmov.s @r0+, fr13
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fmov.s @r0+, fr14
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fmov.s @r0+, fr15
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frchg
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lds.l @r0+, fpscr
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lds.l @r0+, fpul
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#endif /* __SH_FPU_ANY__ */
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mov r8, r0
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add #(oPC), r0
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mov.l @r0+, r2
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lds.l @r0+, pr
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/* Restore T frag. */
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mov.l @r0+, r1
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shlr r1
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/* Skip GBR which is used for thread pointer. */
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add #4, r0
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lds.l @r0+, mach
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lds.l @r0+, macl
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mov r8, r0
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add #(oR9), r0
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mov.l @r0+, r9
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mov.l @r0+, r10
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mov.l @r0+, r11
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mov.l @r0+, r12
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mov.l @r0+, r13
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mov.l @r0+, r14
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mov.l @r0+, r15
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mov r8, r0
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mov.l @(oR0,r0), r1
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mov.l r1, @-r15
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cfi_adjust_cfa_offset(4)
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cfi_rel_offset (r1, 0)
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mov.l r2, @-r15
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cfi_adjust_cfa_offset(4)
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cfi_rel_offset (r2, 0)
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mov.l @(oR1,r0), r1
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mov.l @(oR2,r0), r2
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mov.l @(oR3,r0), r3
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mov.l @(oR4,r0), r4
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mov.l @(oR5,r0), r5
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mov.l @(oR6,r0), r6
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mov.l @(oR7,r0), r7
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mov.l @(oR8,r0), r8
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mov.l @r15+, r0
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cfi_adjust_cfa_offset(-4)
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jmp @r0
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mov.l @r15+, r0
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PSEUDO_END(__swapcontext)
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weak_alias (__swapcontext, swapcontext)
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