drm/amdgpu: fix and cleanup gmc_v11_0_flush_gpu_tlb_pasid
The same PASID can be used by more than one VMID, reset each of them. Use the common KIQ handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 18 additions and 43 deletions
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@ -303,54 +303,27 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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uint16_t pasid, uint32_t flush_type,
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bool all_hub, uint32_t inst)
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{
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uint16_t queried;
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int vmid, i;
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signed long r;
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uint32_t seq;
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uint16_t queried_pasid;
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bool ret;
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struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
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if (amdgpu_emu_mode == 0 && ring->sched.ready) {
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spin_lock(&adev->gfx.kiq[0].ring_lock);
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/* 2 dwords flush + 8 dwords fence */
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amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
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kiq->pmf->kiq_invalidate_tlbs(ring,
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pasid, flush_type, all_hub);
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r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
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if (r) {
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amdgpu_ring_undo(ring);
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spin_unlock(&adev->gfx.kiq[0].ring_lock);
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return -ETIME;
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}
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amdgpu_ring_commit(ring);
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spin_unlock(&adev->gfx.kiq[0].ring_lock);
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r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
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if (r < 1) {
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dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
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return -ETIME;
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}
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return 0;
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}
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for (vmid = 1; vmid < 16; vmid++) {
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bool valid;
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ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
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&queried_pasid);
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if (ret && queried_pasid == pasid) {
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if (all_hub) {
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for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
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gmc_v11_0_flush_gpu_tlb(adev, vmid,
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i, flush_type);
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} else {
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gmc_v11_0_flush_gpu_tlb(adev, vmid,
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AMDGPU_GFXHUB(0), flush_type);
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}
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valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
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&queried);
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if (!valid || queried == pasid)
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continue;
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if (all_hub) {
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for_each_set_bit(i, adev->vmhubs_mask,
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AMDGPU_MAX_VMHUBS)
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gmc_v11_0_flush_gpu_tlb(adev, vmid, i,
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flush_type);
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} else {
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gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
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flush_type);
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}
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}
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return 0;
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}
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@ -920,8 +893,10 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
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static int gmc_v11_0_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;
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/* The sequence of these two function calls matters.*/
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gmc_v11_0_init_golden_registers(adev);
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