drm/amdgpu/jpeg: add support for jpeg DPG mode
Jpeg DPG support for GC IP v11_5_0 Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Saleemkhan Jamadar
Alex Deucher
parent
617efef4af
commit
0a119d53f7
5 changed files with 311 additions and 75 deletions
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@ -36,10 +36,35 @@ static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
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{
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int i, r;
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INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
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mutex_init(&adev->jpeg.jpeg_pg_lock);
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atomic_set(&adev->jpeg.total_submission_cnt, 0);
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
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adev->jpeg.indirect_sram = true;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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if (adev->jpeg.indirect_sram) {
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r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->jpeg.inst[i].dpg_sram_bo,
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&adev->jpeg.inst[i].dpg_sram_gpu_addr,
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&adev->jpeg.inst[i].dpg_sram_cpu_addr);
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if (r) {
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dev_err(adev->dev,
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"JPEG %d (%d) failed to allocate DPG bo\n", i, r);
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return r;
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}
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}
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}
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return 0;
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}
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@ -51,6 +76,11 @@ int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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amdgpu_bo_free_kernel(
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&adev->jpeg.inst[i].dpg_sram_bo,
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&adev->jpeg.inst[i].dpg_sram_gpu_addr,
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(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
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amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
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}
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@ -210,6 +240,7 @@ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
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} else {
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r = 0;
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}
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if (!amdgpu_sriov_vf(adev)) {
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
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@ -296,3 +327,16 @@ int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
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return 0;
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}
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int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
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enum AMDGPU_UCODE_ID ucode_id)
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{
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struct amdgpu_firmware_info ucode = {
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.ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
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.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
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.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
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(uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
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};
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return psp_execute_ip_fw_load(&adev->psp, &ucode);
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}
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@ -32,6 +32,34 @@
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#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
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#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
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#define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
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do { \
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if (!indirect) { \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15( \
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JPEG, GET_INST(JPEG, inst_idx), \
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mmUVD_DPG_LMA_CTL, \
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(UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
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indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} else { \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
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offset; \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
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value; \
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} \
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} while (0)
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#define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \
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({ \
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WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
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(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
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mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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struct amdgpu_jpeg_reg{
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unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
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};
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@ -41,6 +69,11 @@ struct amdgpu_jpeg_inst {
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struct amdgpu_irq_src irq;
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struct amdgpu_irq_src ras_poison_irq;
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struct amdgpu_jpeg_reg external;
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struct amdgpu_bo *dpg_sram_bo;
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struct dpg_pause_state pause_state;
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void *dpg_sram_cpu_addr;
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uint64_t dpg_sram_gpu_addr;
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uint32_t *dpg_sram_curr_addr;
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uint8_t aid_id;
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};
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@ -63,6 +96,7 @@ struct amdgpu_jpeg {
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uint16_t inst_mask;
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uint8_t num_inst_per_aid;
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bool indirect_sram;
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};
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
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@ -82,5 +116,7 @@ int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
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int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,
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struct ras_common_if *ras_block);
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int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
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enum AMDGPU_UCODE_ID ucode_id);
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#endif /*__AMDGPU_JPEG_H__*/
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@ -34,7 +34,17 @@
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#include "vcn/vcn_4_0_5_sh_mask.h"
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#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
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#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
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#define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
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#define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
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#define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
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#define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
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#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
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#define regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET 0x4026
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#define regJPEG_SYS_INT_EN_INTERNAL_OFFSET 0x4141
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#define regJPEG_CGC_CTRL_INTERNAL_OFFSET 0x4161
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#define regJPEG_CGC_GATE_INTERNAL_OFFSET 0x4160
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#define regUVD_NO_OP_INTERNAL_OFFSET 0x0029
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static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
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@ -155,11 +165,18 @@ static int jpeg_v4_0_5_hw_init(void *handle)
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struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
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int r;
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// TODO: Enable ring test with DPG support
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
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DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully under DPG Mode");
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return 0;
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}
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
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if (!r)
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DRM_INFO("JPEG decode initialized successfully under SPG Mode\n");
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return 0;
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}
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@ -227,11 +244,11 @@ static int jpeg_v4_0_5_resume(void *handle)
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return r;
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}
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static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev)
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static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data = 0;
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
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data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
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data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK);
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@ -241,21 +258,21 @@ static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev)
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
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WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
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data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
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data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
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| JPEG_CGC_GATE__JPEG2_DEC_MASK
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| JPEG_CGC_GATE__JMCIF_MASK
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| JPEG_CGC_GATE__JRBBM_MASK);
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
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WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
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}
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static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev)
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static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data = 0;
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
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data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
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data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK;
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@ -265,47 +282,66 @@ static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev)
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
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WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
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data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
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data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
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|JPEG_CGC_GATE__JPEG2_DEC_MASK
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|JPEG_CGC_GATE__JMCIF_MASK
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|JPEG_CGC_GATE__JRBBM_MASK);
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
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WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
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}
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static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev)
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static void jpeg_engine_4_0_5_dpg_clock_gating_mode(struct amdgpu_device *adev,
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int inst_idx, uint8_t indirect)
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{
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uint32_t data = 0;
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
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data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect);
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data = 0;
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WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET,
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data, indirect);
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}
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static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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{
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
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WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
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WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
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1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
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SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
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0, UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
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}
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/* disable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
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WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* keep the JPEG in static PG mode */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
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WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
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return 0;
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}
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static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev)
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static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
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{
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/* enable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
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WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),
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UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
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WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
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WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
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2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
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SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
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1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
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UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
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}
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@ -313,6 +349,90 @@ static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev)
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return 0;
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}
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/**
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* jpeg_v4_0_5_start_dpg_mode - Jpeg start with dpg mode
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*
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* @adev: amdgpu_device pointer
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* @inst_idx: instance number index
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* @indirect: indirectly write sram
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*
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* Start JPEG block with dpg mode
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*/
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static int jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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{
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struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
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uint32_t reg_data = 0;
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/* enable anti hang mechanism */
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reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
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reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
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reg_data |= 0x1;
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WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
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WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG),
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2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS,
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1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
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UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
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}
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reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
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reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
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WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
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if (indirect)
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adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
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(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
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jpeg_engine_4_0_5_dpg_clock_gating_mode(adev, inst_idx, indirect);
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/* MJPEG global tiling registers */
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WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET,
|
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adev->gfx.config.gb_addr_config, indirect);
|
||||
/* enable System Interrupt for JRBC */
|
||||
WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_SYS_INT_EN_INTERNAL_OFFSET,
|
||||
JPEG_SYS_INT_EN__DJRBC_MASK, indirect);
|
||||
|
||||
/* add nop to workaround PSP size check */
|
||||
WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regUVD_NO_OP_INTERNAL_OFFSET, 0, indirect);
|
||||
|
||||
if (indirect)
|
||||
amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);
|
||||
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
|
||||
lower_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
|
||||
upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
|
||||
ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* jpeg_v4_0_5_stop_dpg_mode - Jpeg stop with dpg mode
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @inst_idx: instance number index
|
||||
*
|
||||
* Stop JPEG block with dpg mode
|
||||
*/
|
||||
static void jpeg_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
|
||||
{
|
||||
uint32_t reg_data = 0;
|
||||
|
||||
reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
|
||||
reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
|
||||
WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* jpeg_v4_0_5_start - start JPEG block
|
||||
*
|
||||
|
|
@ -323,52 +443,58 @@ static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev)
|
|||
static int jpeg_v4_0_5_start(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
|
||||
int r;
|
||||
int r, i;
|
||||
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_jpeg(adev, true);
|
||||
|
||||
/* doorbell programming is done for every playback */
|
||||
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
||||
(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
/* doorbell programming is done for every playback */
|
||||
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
||||
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
|
||||
|
||||
WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
|
||||
ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
|
||||
VCN_JPEG_DB_CTRL__EN_MASK);
|
||||
WREG32_SOC15(VCN, i, regVCN_JPEG_DB_CTRL,
|
||||
ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
|
||||
VCN_JPEG_DB_CTRL__EN_MASK);
|
||||
|
||||
/* disable power gating */
|
||||
r = jpeg_v4_0_5_disable_static_power_gating(adev);
|
||||
if (r)
|
||||
return r;
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
|
||||
r = jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* JPEG disable CGC */
|
||||
jpeg_v4_0_5_disable_clock_gating(adev);
|
||||
/* disable power gating */
|
||||
r = jpeg_v4_0_5_disable_static_power_gating(adev, i);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* MJPEG global tiling registers */
|
||||
WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
|
||||
adev->gfx.config.gb_addr_config);
|
||||
/* JPEG disable CGC */
|
||||
jpeg_v4_0_5_disable_clock_gating(adev, i);
|
||||
|
||||
/* MJPEG global tiling registers */
|
||||
WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG,
|
||||
adev->gfx.config.gb_addr_config);
|
||||
|
||||
/* enable JMI channel */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
|
||||
~UVD_JMI_CNTL__SOFT_RESET_MASK);
|
||||
/* enable JMI channel */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,
|
||||
~UVD_JMI_CNTL__SOFT_RESET_MASK);
|
||||
|
||||
/* enable System Interrupt for JRBC */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
|
||||
JPEG_SYS_INT_EN__DJRBC_MASK,
|
||||
~JPEG_SYS_INT_EN__DJRBC_MASK);
|
||||
/* enable System Interrupt for JRBC */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),
|
||||
JPEG_SYS_INT_EN__DJRBC_MASK,
|
||||
~JPEG_SYS_INT_EN__DJRBC_MASK);
|
||||
|
||||
WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
|
||||
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
|
||||
WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
|
||||
lower_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
|
||||
upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
|
||||
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
|
||||
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
|
||||
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
|
||||
ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
|
||||
WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_VMID, 0);
|
||||
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
|
||||
WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
|
||||
lower_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
|
||||
upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_RPTR, 0);
|
||||
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0);
|
||||
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, 0x00000002L);
|
||||
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
|
||||
ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -382,19 +508,26 @@ static int jpeg_v4_0_5_start(struct amdgpu_device *adev)
|
|||
*/
|
||||
static int jpeg_v4_0_5_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
int r;
|
||||
int r, i;
|
||||
|
||||
/* reset JMI */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
|
||||
UVD_JMI_CNTL__SOFT_RESET_MASK,
|
||||
~UVD_JMI_CNTL__SOFT_RESET_MASK);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
|
||||
|
||||
jpeg_v4_0_5_enable_clock_gating(adev);
|
||||
jpeg_v4_0_5_stop_dpg_mode(adev, i);
|
||||
continue;
|
||||
}
|
||||
/* reset JMI */
|
||||
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),
|
||||
UVD_JMI_CNTL__SOFT_RESET_MASK,
|
||||
~UVD_JMI_CNTL__SOFT_RESET_MASK);
|
||||
|
||||
/* enable power gating */
|
||||
r = jpeg_v4_0_5_enable_static_power_gating(adev);
|
||||
if (r)
|
||||
return r;
|
||||
jpeg_v4_0_5_enable_clock_gating(adev, i);
|
||||
|
||||
/* enable power gating */
|
||||
r = jpeg_v4_0_5_enable_static_power_gating(adev, i);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_jpeg(adev, false);
|
||||
|
|
@ -478,13 +611,20 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
||||
int i;
|
||||
|
||||
if (enable) {
|
||||
if (!jpeg_v4_0_5_is_idle(handle))
|
||||
return -EBUSY;
|
||||
jpeg_v4_0_5_enable_clock_gating(adev);
|
||||
} else {
|
||||
jpeg_v4_0_5_disable_clock_gating(adev);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
if (enable) {
|
||||
if (!jpeg_v4_0_5_is_idle(handle))
|
||||
return -EBUSY;
|
||||
|
||||
jpeg_v4_0_5_enable_clock_gating(adev, i);
|
||||
} else {
|
||||
jpeg_v4_0_5_disable_clock_gating(adev, i);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -589,8 +729,15 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
|
|||
|
||||
static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;
|
||||
DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;
|
||||
DRM_DEV_INFO(adev->dev, "JPEG%d decode is enabled in VM mode\n", i);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = {
|
||||
|
|
@ -599,8 +746,15 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = {
|
|||
|
||||
static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->jpeg.inst->irq.num_types = 1;
|
||||
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_5_irq_funcs;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
adev->jpeg.inst[i].irq.num_types = 1;
|
||||
adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs;
|
||||
}
|
||||
}
|
||||
|
||||
const struct amdgpu_ip_block_version jpeg_v4_0_5_ip_block = {
|
||||
|
|
|
|||
|
|
@ -711,6 +711,7 @@ static int soc21_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_BIF_MGCG |
|
||||
AMD_CG_SUPPORT_BIF_LS;
|
||||
adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
|
||||
AMD_PG_SUPPORT_JPEG_DPG |
|
||||
AMD_PG_SUPPORT_VCN |
|
||||
AMD_PG_SUPPORT_JPEG |
|
||||
AMD_PG_SUPPORT_GFX_PG;
|
||||
|
|
|
|||
|
|
@ -174,6 +174,7 @@ enum amd_powergating_state {
|
|||
#define AMD_PG_SUPPORT_ATHUB (1 << 16)
|
||||
#define AMD_PG_SUPPORT_JPEG (1 << 17)
|
||||
#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)
|
||||
#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)
|
||||
|
||||
/**
|
||||
* enum PP_FEATURE_MASK - Used to mask power play features.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue