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mtd: rawnand: qcom: use FIELD_PREP and GENMASK

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Use the bitfield macro FIELD_PREP, and GENMASK to
do the shift and mask in one go. This makes the code
more readable.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Md Sadre Alam 2024-11-20 14:45:03 +05:30 • committed by Miquel Raynal
parent fdf3ee5c6e
commit 0c08080fd7
2 changed files with 63 additions and 57 deletions
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89
drivers/mtd/nand/raw/qcom_nandc.c
View file

@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
(num_cw - 1) << CW_PER_PAGE);
cfg1 = cpu_to_le32(host->cfg1_raw);
ecc_bch_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
ecc_bch_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
}
nandc->regs->cmd = cmd;
@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
host->cw_size = host->cw_data + ecc->bytes;
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
| host->cw_data << UD_SIZE_BYTES
| 0 << DISABLE_STATUS_AFTER_WRITE
| 5 << NUM_ADDR_CYCLES
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
| 0 << STATUS_BFR_READ
| 1 << SET_RD_MODE_AFTER_STATUS
| host->spare_bytes << SPARE_SIZE_BYTES;
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) |
FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 0) |
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) |
FIELD_PREP(STATUS_BFR_READ, 0) |
FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes);
host->cfg1 = 7 << NAND_RECOVERY_CYCLES
| 0 << CS_ACTIVE_BSY
| bad_block_byte << BAD_BLOCK_BYTE_NUM
| 0 << BAD_BLOCK_IN_SPARE_AREA
| 2 << WR_RD_BSY_GAP
| wide_bus << WIDE_FLASH
| host->bch_enabled << ENABLE_BCH_ECC;
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
FIELD_PREP(WIDE_FLASH, wide_bus) |
FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled);
host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
| host->cw_size << UD_SIZE_BYTES
| 5 << NUM_ADDR_CYCLES
| 0 << SPARE_SIZE_BYTES;
host->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) |
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
| 0 << CS_ACTIVE_BSY
| 17 << BAD_BLOCK_BYTE_NUM
| 1 << BAD_BLOCK_IN_SPARE_AREA
| 2 << WR_RD_BSY_GAP
| wide_bus << WIDE_FLASH
| 1 << DEV0_CFG1_ECC_DISABLE;
host->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
FIELD_PREP(CS_ACTIVE_BSY, 0) |
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
FIELD_PREP(WIDE_FLASH, wide_bus) |
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
| 0 << ECC_SW_RESET
| host->cw_data << ECC_NUM_DATA_BYTES
| 1 << ECC_FORCE_CLK_OPEN
| ecc_mode << ECC_MODE
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
host->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled) |
FIELD_PREP(ECC_SW_RESET, 0) |
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) |
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
FIELD_PREP(ECC_MODE_MASK, ecc_mode) |
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw);
if (!nandc->props->qpic_version2)
host->ecc_buf_cfg = 0x203 << NUM_STEPS;
@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_
nandc->regs->addr0 = 0;
nandc->regs->addr1 = 0;
nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE |
512 << UD_SIZE_BYTES |
5 << NUM_ADDR_CYCLES |
0 << SPARE_SIZE_BYTES);
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES |
0 << CS_ACTIVE_BSY |
17 << BAD_BLOCK_BYTE_NUM |
1 << BAD_BLOCK_IN_SPARE_AREA |
2 << WR_RD_BSY_GAP |
0 << WIDE_FLASH |
1 << DEV0_CFG1_ECC_DISABLE);
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
FIELD_PREP(CS_ACTIVE_BSY, 0) |
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
FIELD_PREP(WIDE_FLASH, 0) |
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
if (!nandc->props->qpic_version2)
nandc->regs->ecc_buf_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
if (!nandc->props->qpic_version2) {

31
include/linux/mtd/nand-qpic-common.h
View file

@ -70,35 +70,42 @@
#define BS_CORRECTABLE_ERR_MSK 0x1f
/* NAND_DEVn_CFG0 bits */
#define DISABLE_STATUS_AFTER_WRITE 4
#define DISABLE_STATUS_AFTER_WRITE BIT(4)
#define CW_PER_PAGE 6
#define CW_PER_PAGE_MASK GENMASK(8, 6)
#define UD_SIZE_BYTES 9
#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
#define ECC_PARITY_SIZE_BYTES_RS 19
#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)
#define SPARE_SIZE_BYTES 23
#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
#define NUM_ADDR_CYCLES 27
#define STATUS_BFR_READ 30
#define SET_RD_MODE_AFTER_STATUS 31
#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)
#define STATUS_BFR_READ BIT(30)
#define SET_RD_MODE_AFTER_STATUS BIT(31)
/* NAND_DEVn_CFG0 bits */
#define DEV0_CFG1_ECC_DISABLE 0
#define WIDE_FLASH 1
#define DEV0_CFG1_ECC_DISABLE BIT(0)
#define WIDE_FLASH BIT(1)
#define NAND_RECOVERY_CYCLES 2
#define CS_ACTIVE_BSY 5
#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)
#define CS_ACTIVE_BSY BIT(5)
#define BAD_BLOCK_BYTE_NUM 6
#define BAD_BLOCK_IN_SPARE_AREA 16
#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)
#define BAD_BLOCK_IN_SPARE_AREA BIT(16)
#define WR_RD_BSY_GAP 17
#define ENABLE_BCH_ECC 27
#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)
#define ENABLE_BCH_ECC BIT(27)
/* NAND_DEV0_ECC_CFG bits */
#define ECC_CFG_ECC_DISABLE 0
#define ECC_SW_RESET 1
#define ECC_CFG_ECC_DISABLE BIT(0)
#define ECC_SW_RESET BIT(1)
#define ECC_MODE 4
#define ECC_MODE_MASK GENMASK(5, 4)
#define ECC_PARITY_SIZE_BYTES_BCH 8
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
#define ECC_NUM_DATA_BYTES 16
#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
#define ECC_FORCE_CLK_OPEN 30
#define ECC_FORCE_CLK_OPEN BIT(30)
/* NAND_DEV_CMD1 bits */
#define READ_ADDR 0