dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema
Convert Renesas PCIe Host controller bindings documentation to json-schema. Note that some compatible doesn't contain on the original documentation so that incremental patches are required for it. Link: https://lore.kernel.org/r/1604455096-13923-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
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Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
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Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car PCIe Host
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maintainers:
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- Marek Vasut <marek.vasut+renesas@gmail.com>
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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allOf:
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- $ref: pci-bus.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,pcie-r8a7742 # RZ/G1H
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- renesas,pcie-r8a7743 # RZ/G1M
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- renesas,pcie-r8a7744 # RZ/G1N
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- renesas,pcie-r8a7790 # R-Car H2
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- renesas,pcie-r8a7791 # R-Car M2-W
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- renesas,pcie-r8a7793 # R-Car M2-N
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- const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,pcie-r8a774a1 # RZ/G2M
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- renesas,pcie-r8a774b1 # RZ/G2N
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- renesas,pcie-r8a774c0 # RZ/G2E
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- renesas,pcie-r8a7795 # R-Car H3
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- renesas,pcie-r8a7796 # R-Car M3-W
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- renesas,pcie-r8a77961 # R-Car M3-W+
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- renesas,pcie-r8a77980 # R-Car V3H
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- renesas,pcie-r8a77990 # R-Car E3
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- const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
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reg:
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maxItems: 1
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interrupts:
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minItems: 3
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maxItems: 3
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7791-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
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<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
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<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
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<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
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<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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resets = <&cpg 319>;
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};
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};
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* Renesas R-Car PCIe interface
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Required properties:
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compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
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"renesas,pcie-r8a7743" for the R8A7743 SoC;
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"renesas,pcie-r8a7744" for the R8A7744 SoC;
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"renesas,pcie-r8a774a1" for the R8A774A1 SoC;
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"renesas,pcie-r8a774b1" for the R8A774B1 SoC;
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"renesas,pcie-r8a774c0" for the R8A774C0 SoC;
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"renesas,pcie-r8a7779" for the R8A7779 SoC;
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"renesas,pcie-r8a7790" for the R8A7790 SoC;
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"renesas,pcie-r8a7791" for the R8A7791 SoC;
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"renesas,pcie-r8a7793" for the R8A7793 SoC;
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"renesas,pcie-r8a7795" for the R8A7795 SoC;
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"renesas,pcie-r8a7796" for the R8A77960 SoC;
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"renesas,pcie-r8a77961" for the R8A77961 SoC;
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"renesas,pcie-r8a77980" for the R8A77980 SoC;
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"renesas,pcie-r8a77990" for the R8A77990 SoC;
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"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
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RZ/G1 compatible device.
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"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or
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RZ/G2 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: base address and length of the PCIe controller registers.
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- bus-range: PCI bus numbers covered
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions.
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- dma-ranges: ranges for the inbound memory regions.
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- interrupts: two interrupt sources for MSI interrupts, followed by interrupt
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source for hardware related interrupts (e.g. link speed change).
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt numbers.
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- clocks: from common clock binding: clock specifiers for the PCIe controller
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and PCIe bus clocks.
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- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
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Optional properties:
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- phys: from common PHY binding: PHY phandle and specifier (only make sense
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for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
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- phy-names: from common PHY binding: should be "pcie".
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Example:
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SoC-specific DT Entry:
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
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0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
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0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
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0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
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0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 116 4>;
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clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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};
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