amd64_edac: Fix K8 revD and later chip select sizes
Fix DRAM chip select sizes calculation for K8, revisions D and E. Reported-by: Niklas Söderlund <niklas.soderlund@ericsson.com Link: http://lkml.kernel.org/r/1320849178-23340-1-git-send-email-niklas.soderlund@ericsson.com Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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1 changed files with 28 additions and 4 deletions
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@ -1132,12 +1132,36 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
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return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
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}
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}
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else if (pvt->ext_model >= K8_REV_D) {
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else if (pvt->ext_model >= K8_REV_D) {
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unsigned diff;
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WARN_ON(cs_mode > 10);
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WARN_ON(cs_mode > 10);
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if (cs_mode == 3 || cs_mode == 8)
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/*
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return 32 << (cs_mode - 1);
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* the below calculation, besides trying to win an obfuscated C
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else
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* contest, maps cs_mode values to DIMM chip select sizes. The
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return 32 << cs_mode;
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* mappings are:
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*
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* cs_mode CS size (mb)
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* ======= ============
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* 0 32
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* 1 64
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* 2 128
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* 3 128
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* 4 256
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* 5 512
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* 6 256
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* 7 512
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* 8 1024
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* 9 1024
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* 10 2048
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*
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* Basically, it calculates a value with which to shift the
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* smallest CS size of 32MB.
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*
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* ddr[23]_cs_size have a similar purpose.
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*/
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diff = cs_mode/3 + (unsigned)(cs_mode > 5);
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return 32 << (cs_mode - diff);
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}
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}
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else {
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else {
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WARN_ON(cs_mode > 6);
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WARN_ON(cs_mode > 6);
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