net: ftgmac100: Fix Aspeed ast2600 TX hang issue
The new HW arbitration feature on Aspeed ast2600 will cause MAC TX to
hang when handling scatter-gather DMA. Disable the problematic feature
by setting MAC register 0x58 bit28 and bit27.
Fixes: 39bfab8844
("net: ftgmac100: Add support for DT phy-handle property")
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
ec78e31852
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137d23cea1
2 changed files with 13 additions and 0 deletions
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@ -1817,6 +1817,11 @@ static int ftgmac100_probe(struct platform_device *pdev)
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priv->rxdes0_edorr_mask = BIT(30);
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priv->rxdes0_edorr_mask = BIT(30);
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priv->txdes0_edotr_mask = BIT(30);
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priv->txdes0_edotr_mask = BIT(30);
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priv->is_aspeed = true;
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priv->is_aspeed = true;
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/* Disable ast2600 problematic HW arbitration */
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if (of_device_is_compatible(np, "aspeed,ast2600-mac")) {
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iowrite32(FTGMAC100_TM_DEFAULT,
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priv->base + FTGMAC100_OFFSET_TM);
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}
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} else {
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} else {
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priv->rxdes0_edorr_mask = BIT(15);
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priv->rxdes0_edorr_mask = BIT(15);
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priv->txdes0_edotr_mask = BIT(15);
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priv->txdes0_edotr_mask = BIT(15);
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@ -169,6 +169,14 @@
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#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
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#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
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#define FTGMAC100_MACCR_SW_RST (1 << 31)
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#define FTGMAC100_MACCR_SW_RST (1 << 31)
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/*
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* test mode control register
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*/
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#define FTGMAC100_TM_RQ_TX_VALID_DIS (1 << 28)
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#define FTGMAC100_TM_RQ_RR_IDLE_PREV (1 << 27)
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#define FTGMAC100_TM_DEFAULT \
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(FTGMAC100_TM_RQ_TX_VALID_DIS | FTGMAC100_TM_RQ_RR_IDLE_PREV)
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/*
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/*
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* PHY control register
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* PHY control register
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*/
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*/
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