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iio: adc: aspeed: Add func to set sampling rate.

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Add the function to set the sampling rate and keep the sampling period
for a driver used to wait the fresh value.
In addition, since the ADC clock is required when initializing the ADC
device, move clk_prepare_enable ahead of the initialization phase.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20210922081520.30580-9-billy_tsai@aspeedtech.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Billy Tsai 2021-09-22 16:15:17 +08:00 • committed by Jonathan Cameron
parent 90f9647753
commit 13d4f9df33
1 changed files with 39 additions and 19 deletions
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58
drivers/iio/adc/aspeed_adc.c
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@ -73,6 +73,12 @@
#define ASPEED_ADC_INIT_POLLING_TIME 500 #define ASPEED_ADC_INIT_POLLING_TIME 500
#define ASPEED_ADC_INIT_TIMEOUT 500000 #define ASPEED_ADC_INIT_TIMEOUT 500000
/*
* When the sampling rate is too high, the ADC may not have enough charging
* time, resulting in a low voltage value. Thus, the default uses a slow
* sampling rate for most use cases.
*/
#define ASPEED_ADC_DEF_SAMPLING_RATE 65000
struct aspeed_adc_model_data { struct aspeed_adc_model_data {
const char *model_name; const char *model_name;
@ -96,6 +102,7 @@ struct aspeed_adc_data {
struct clk_hw *clk_scaler; struct clk_hw *clk_scaler;
struct reset_control *rst; struct reset_control *rst;
int vref_mv; int vref_mv;
u32 sample_period_ns;
}; };
#define ASPEED_CHAN(_idx, _data_reg_addr) { \ #define ASPEED_CHAN(_idx, _data_reg_addr) { \
@ -127,6 +134,24 @@ static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
ASPEED_CHAN(15, 0x2E), ASPEED_CHAN(15, 0x2E),
}; };
static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
{
struct aspeed_adc_data *data = iio_priv(indio_dev);
if (rate < data->model_data->min_sampling_rate ||
rate > data->model_data->max_sampling_rate)
return -EINVAL;
/* Each sampling needs 12 clocks to convert.*/
clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
rate = clk_get_rate(data->clk_scaler->clk);
data->sample_period_ns = DIV_ROUND_UP_ULL(
(u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
data->sample_period_ns);
return 0;
}
static int aspeed_adc_read_raw(struct iio_dev *indio_dev, static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, struct iio_chan_spec const *chan,
int *val, int *val2, long mask) int *val, int *val2, long mask)
@ -157,17 +182,9 @@ static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, struct iio_chan_spec const *chan,
int val, int val2, long mask) int val, int val2, long mask)
{ {
struct aspeed_adc_data *data = iio_priv(indio_dev);
switch (mask) { switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ: case IIO_CHAN_INFO_SAMP_FREQ:
if (val < data->model_data->min_sampling_rate || return aspeed_adc_set_sampling_rate(indio_dev, val);
val > data->model_data->max_sampling_rate)
return -EINVAL;
clk_set_rate(data->clk_scaler->clk,
val * ASPEED_CLOCKS_PER_SAMPLE);
return 0;
case IIO_CHAN_INFO_SCALE: case IIO_CHAN_INFO_SCALE:
case IIO_CHAN_INFO_RAW: case IIO_CHAN_INFO_RAW:
@ -391,6 +408,19 @@ static int aspeed_adc_probe(struct platform_device *pdev)
if (ret) if (ret)
return ret; return ret;
ret = clk_prepare_enable(data->clk_scaler->clk);
if (ret)
return ret;
ret = devm_add_action_or_reset(data->dev,
aspeed_adc_clk_disable_unprepare,
data->clk_scaler->clk);
if (ret)
return ret;
ret = aspeed_adc_set_sampling_rate(indio_dev,
ASPEED_ADC_DEF_SAMPLING_RATE);
if (ret)
return ret;
adc_engine_control_reg_val = adc_engine_control_reg_val =
readl(data->base + ASPEED_REG_ENGINE_CONTROL); readl(data->base + ASPEED_REG_ENGINE_CONTROL);
adc_engine_control_reg_val |= adc_engine_control_reg_val |=
@ -417,16 +447,6 @@ static int aspeed_adc_probe(struct platform_device *pdev)
return ret; return ret;
} }
ret = clk_prepare_enable(data->clk_scaler->clk);
if (ret)
return ret;
ret = devm_add_action_or_reset(data->dev,
aspeed_adc_clk_disable_unprepare,
data->clk_scaler->clk);
if (ret)
return ret;
/* Start all channels in normal mode. */ /* Start all channels in normal mode. */
adc_engine_control_reg_val = adc_engine_control_reg_val =
readl(data->base + ASPEED_REG_ENGINE_CONTROL); readl(data->base + ASPEED_REG_ENGINE_CONTROL);