drm/stm: dsi: expose DSI PHY internal clock
DSISRC __________ __\_ | \ pll4_p_ck ->| 1 |____dsi_k ck_dsi_phy ->| 0 | |____/ A DSI clock is missing in the clock framework. Looking at the clk_summary, it appears that 'ck_dsi_phy' is not implemented. Since the DSI kernel clock is based on the internal DSI pll. The common clock driver can not directly expose this 'ck_dsi_phy' clock because it does not contain any common registers with the DSI. Thus it needs to be done directly within the DSI phy driver. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Tested-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129104106.43141-4-raphael.gallais-pou@foss.st.com
This commit is contained in:
Raphael Gallais-Pou
Philippe Cornu
parent
b0e83c2c85
commit
185f99b614
1 changed files with 216 additions and 31 deletions
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@ -7,7 +7,9 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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@ -77,9 +79,12 @@ enum dsi_color {
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struct dw_mipi_dsi_stm {
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void __iomem *base;
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struct device *dev;
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struct clk *pllref_clk;
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struct clk *pclk;
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struct clk_hw txbyte_clk;
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struct dw_mipi_dsi *dsi;
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struct dw_mipi_dsi_plat_data pdata;
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u32 hw_version;
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int lane_min_kbps;
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int lane_max_kbps;
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@ -196,29 +201,198 @@ static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
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return 0;
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}
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static int dw_mipi_dsi_phy_init(void *priv_data)
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#define clk_to_dw_mipi_dsi_stm(clk) \
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container_of(clk, struct dw_mipi_dsi_stm, txbyte_clk)
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static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
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DRM_DEBUG_DRIVER("\n");
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/* Disable the DSI PLL */
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dsi_clear(dsi, DSI_WRPCR, WRPCR_PLLEN);
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/* Disable the regulator */
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dsi_clear(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
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}
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static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
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{
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
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u32 val;
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int ret;
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DRM_DEBUG_DRIVER("\n");
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/* Enable the regulator */
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dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
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SLEEP_US, TIMEOUT_US);
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ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_RRS,
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SLEEP_US, TIMEOUT_US);
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if (ret)
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DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
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/* Enable the DSI PLL & wait for its lock */
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dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
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SLEEP_US, TIMEOUT_US);
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ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
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SLEEP_US, TIMEOUT_US);
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if (ret)
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DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
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return 0;
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}
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static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
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{
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
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return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
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}
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static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
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unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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u32 val;
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DRM_DEBUG_DRIVER("\n");
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pll_in_khz = (unsigned int)(parent_rate / 1000);
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val = dsi_read(dsi, DSI_WRPCR);
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idf = (val & WRPCR_IDF) >> 11;
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if (!idf)
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idf = 1;
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ndiv = (val & WRPCR_NDIV) >> 2;
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odf = int_pow(2, (val & WRPCR_ODF) >> 16);
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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return (unsigned long)pll_out_khz * 1000;
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}
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static long dw_mipi_dsi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
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unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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int ret;
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DRM_DEBUG_DRIVER("\n");
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pll_in_khz = (unsigned int)(*parent_rate / 1000);
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/* Compute best pll parameters */
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idf = 0;
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ndiv = 0;
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odf = 0;
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ret = dsi_pll_get_params(dsi, pll_in_khz, rate / 1000,
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&idf, &ndiv, &odf);
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if (ret)
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DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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return pll_out_khz * 1000;
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}
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static int dw_mipi_dsi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
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unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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int ret;
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u32 val;
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DRM_DEBUG_DRIVER("\n");
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pll_in_khz = (unsigned int)(parent_rate / 1000);
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/* Compute best pll parameters */
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idf = 0;
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ndiv = 0;
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odf = 0;
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ret = dsi_pll_get_params(dsi, pll_in_khz, rate / 1000, &idf, &ndiv, &odf);
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if (ret)
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DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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/* Set the PLL division factors */
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dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
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(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
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/* Compute uix4 & set the bit period in high-speed mode */
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val = 4000000 / pll_out_khz;
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dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
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return 0;
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}
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static void dw_mipi_dsi_clk_unregister(void *data)
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{
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struct dw_mipi_dsi_stm *dsi = data;
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DRM_DEBUG_DRIVER("\n");
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of_clk_del_provider(dsi->dev->of_node);
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clk_hw_unregister(&dsi->txbyte_clk);
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}
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static const struct clk_ops dw_mipi_dsi_stm_clk_ops = {
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.enable = dw_mipi_dsi_clk_enable,
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.disable = dw_mipi_dsi_clk_disable,
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.is_enabled = dw_mipi_dsi_clk_is_enabled,
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.recalc_rate = dw_mipi_dsi_clk_recalc_rate,
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.round_rate = dw_mipi_dsi_clk_round_rate,
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.set_rate = dw_mipi_dsi_clk_set_rate,
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};
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static struct clk_init_data cdata_init = {
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.name = "ck_dsi_phy",
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.ops = &dw_mipi_dsi_stm_clk_ops,
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.parent_names = (const char * []) {"ck_hse"},
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.num_parents = 1,
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};
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static int dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm *dsi,
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struct device *dev)
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{
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struct device_node *node = dev->of_node;
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int ret;
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DRM_DEBUG_DRIVER("Registering clk\n");
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dsi->txbyte_clk.init = &cdata_init;
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ret = clk_hw_register(dev, &dsi->txbyte_clk);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get,
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&dsi->txbyte_clk);
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if (ret)
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clk_hw_unregister(&dsi->txbyte_clk);
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return ret;
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}
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static int dw_mipi_dsi_phy_init(void *priv_data)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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int ret;
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ret = clk_prepare_enable(dsi->txbyte_clk.clk);
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return ret;
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}
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static void dw_mipi_dsi_phy_power_on(void *priv_data)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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@ -235,6 +409,8 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
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DRM_DEBUG_DRIVER("\n");
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clk_disable_unprepare(dsi->txbyte_clk.clk);
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/* Disable the DSI wrapper */
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dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
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}
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@ -245,9 +421,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
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unsigned int *lane_mbps)
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{
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struct dw_mipi_dsi_stm *dsi = priv_data;
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unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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unsigned int pll_in_khz, pll_out_khz;
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int ret, bpp;
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u32 val;
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pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
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@ -268,25 +443,10 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
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DRM_WARN("Warning min phy mbps is used\n");
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}
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/* Compute best pll parameters */
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idf = 0;
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ndiv = 0;
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odf = 0;
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ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
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&idf, &ndiv, &odf);
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ret = clk_set_rate((dsi->txbyte_clk.clk), pll_out_khz * 1000);
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if (ret)
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DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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/* Set the PLL division factors */
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dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
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(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
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/* Compute uix4 & set the bit period in high-speed mode */
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val = 4000000 / pll_out_khz;
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dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
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DRM_DEBUG_DRIVER("ERROR Could not set rate of %d to %s clk->name",
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pll_out_khz, clk_hw_get_name(&dsi->txbyte_clk));
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/* Select video mode by resetting DSIM bit */
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dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
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@ -445,6 +605,7 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_mipi_dsi_stm *dsi;
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const struct dw_mipi_dsi_plat_data *pdata = of_device_get_match_data(dev);
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int ret;
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dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
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@ -514,18 +675,41 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
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dsi->lane_max_kbps *= 2;
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}
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dw_mipi_dsi_stm_plat_data.base = dsi->base;
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dw_mipi_dsi_stm_plat_data.priv_data = dsi;
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dsi->pdata = *pdata;
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dsi->pdata.base = dsi->base;
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dsi->pdata.priv_data = dsi;
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dsi->pdata.max_data_lanes = 2;
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dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops;
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platform_set_drvdata(pdev, dsi);
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dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
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dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata);
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if (IS_ERR(dsi->dsi)) {
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ret = PTR_ERR(dsi->dsi);
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dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n");
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goto err_dsi_probe;
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}
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/*
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* We need to wait for the generic bridge to probe before enabling and
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* register the internal pixel clock.
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*/
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ret = clk_prepare_enable(dsi->pclk);
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if (ret) {
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DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
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goto err_dsi_probe;
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}
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ret = dw_mipi_dsi_clk_register(dsi, dev);
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if (ret) {
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DRM_ERROR("Failed to register DSI pixel clock: %d\n", ret);
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clk_disable_unprepare(dsi->pclk);
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goto err_dsi_probe;
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}
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clk_disable_unprepare(dsi->pclk);
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return 0;
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err_dsi_probe:
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@ -542,12 +726,13 @@ static void dw_mipi_dsi_stm_remove(struct platform_device *pdev)
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dw_mipi_dsi_remove(dsi->dsi);
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clk_disable_unprepare(dsi->pllref_clk);
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dw_mipi_dsi_clk_unregister(dsi);
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regulator_disable(dsi->vdd_supply);
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}
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static int dw_mipi_dsi_stm_suspend(struct device *dev)
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{
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struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
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struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
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DRM_DEBUG_DRIVER("\n");
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@ -560,7 +745,7 @@ static int dw_mipi_dsi_stm_suspend(struct device *dev)
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static int dw_mipi_dsi_stm_resume(struct device *dev)
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{
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struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
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struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
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int ret;
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DRM_DEBUG_DRIVER("\n");
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