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ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions

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Replace the hardcoded clock indices by R9A06G032_CLK_* symbols.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2018-08-28 17:12:31 +02:00 • committed by Simon Horman
parent af69e34040
commit 1926bd6bf2
1 changed files with 4 additions and 3 deletions
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7
arch/arm/boot/dts/r9a06g032.dtsi
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@ -7,6 +7,7 @@
*/ */
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
/ { / {
compatible = "renesas,r9a06g032"; compatible = "renesas,r9a06g032";
@ -21,14 +22,14 @@
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
reg = <0>; reg = <0>;
clocks = <&sysctrl 84>; clocks = <&sysctrl R9A06G032_CLK_A7MP>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
reg = <1>; reg = <1>;
clocks = <&sysctrl 84>; clocks = <&sysctrl R9A06G032_CLK_A7MP>;
enable-method = "renesas,r9a06g032-smp"; enable-method = "renesas,r9a06g032-smp";
cpu-release-addr = <0 0x4000c204>; cpu-release-addr = <0 0x4000c204>;
}; };
@ -82,7 +83,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&sysctrl 146>; clocks = <&sysctrl R9A06G032_CLK_UART0>;
clock-names = "baudclk"; clock-names = "baudclk";
status = "disabled"; status = "disabled";
}; };