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drm/amdgpu/vcn: remove manual instance setting

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Handled by IP discovery now.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2021-08-09 12:41:29 -04:00
parent fe323f039d
commit 1b592d00b4
4 changed files with 2 additions and 6 deletions
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1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
View file

@ -66,7 +66,6 @@ static int vcn_v1_0_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->vcn.num_vcn_inst = 1;
adev->vcn.num_enc_rings = 2; adev->vcn.num_enc_rings = 2;
vcn_v1_0_set_dec_ring_funcs(adev); vcn_v1_0_set_dec_ring_funcs(adev);

1
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View file

@ -69,7 +69,6 @@ static int vcn_v2_0_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->vcn.num_vcn_inst = 1;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
adev->vcn.num_enc_rings = 1; adev->vcn.num_enc_rings = 1;
else else

2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View file

@ -83,7 +83,7 @@ static int vcn_v2_5_early_init(void *handle)
} else { } else {
u32 harvest; u32 harvest;
int i; int i;
adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)

4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View file

@ -98,7 +98,6 @@ static int vcn_v3_0_early_init(void *handle)
if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) { if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
u32 harvest; u32 harvest;
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
@ -109,8 +108,7 @@ static int vcn_v3_0_early_init(void *handle)
AMDGPU_VCN_HARVEST_VCN1)) AMDGPU_VCN_HARVEST_VCN1))
/* both instances are harvested, disable the block */ /* both instances are harvested, disable the block */
return -ENOENT; return -ENOENT;
} else }
adev->vcn.num_vcn_inst = 1;
if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33)) if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
adev->vcn.num_enc_rings = 0; adev->vcn.num_enc_rings = 0;