iwlwifi: mvm: add support for IMR based on platform
Driver needs to enable IMR which is needed for debug on certain platforms, so add a device config flag to set it. Signed-off-by: Mukesh Sisodiya <mukesh.sisodiya@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20220304131517.0b96b2760503.I08bc741c8c497a2edbe4784cdab6abd8d04c62f3@changeid Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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5053a45110
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5 changed files with 28 additions and 4 deletions
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@ -391,6 +391,21 @@ const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
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.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
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};
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const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
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.mq_rx_supported = true,
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.use_tfh = true,
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.rf_id = true,
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.gen2 = true,
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.device_family = IWL_DEVICE_FAMILY_AX210,
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.base_params = &iwl_ax210_base_params,
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.umac_prph_offset = 0x300000,
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.integrated = true,
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.low_latency_xtal = true,
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.xtal_latency = 12000,
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.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
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.imr_enabled = true,
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};
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/*
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* If the device doesn't support HE, no need to have that many buffers.
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* 22000 devices can split multiple frames into a single RB, so fewer are
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@ -260,6 +260,7 @@ enum iwl_cfg_trans_ltr_delay {
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* @integrated: discrete or integrated
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* @low_latency_xtal: use the low latency xtal if supported
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* @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
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* @imr_enabled: use the IMR if supported.
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*/
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struct iwl_cfg_trans_params {
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const struct iwl_base_params *base_params;
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@ -274,7 +275,8 @@ struct iwl_cfg_trans_params {
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integrated:1,
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low_latency_xtal:1,
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bisr_workaround:1,
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ltr_delay:2;
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ltr_delay:2,
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imr_enabled:1;
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};
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/**
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@ -491,6 +493,7 @@ extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
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extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
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extern const char iwl9162_name[];
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, 2020-2021 Intel Corporation
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* Copyright (C) 2018, 2020-2022 Intel Corporation
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*/
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#ifndef __iwl_context_info_file_gen3_h__
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#define __iwl_context_info_file_gen3_h__
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@ -34,6 +34,7 @@ enum iwl_prph_scratch_mtr_format {
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/**
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* enum iwl_prph_scratch_flags - PRPH scratch control flags
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* @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
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* @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
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* @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
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* in hwm config.
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@ -55,6 +56,7 @@ enum iwl_prph_scratch_mtr_format {
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* @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
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*/
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enum iwl_prph_scratch_flags {
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IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1),
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IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4),
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IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8),
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IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9),
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2018-2021 Intel Corporation
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* Copyright (C) 2018-2022 Intel Corporation
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*/
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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@ -125,6 +125,9 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
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control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
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if (trans->trans_cfg->imr_enabled)
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control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN;
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/* initialize RX default queue */
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prph_sc_ctrl->rbd_cfg.free_rbd_addr =
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cpu_to_le64(trans_pcie->rxq->bd_dma);
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@ -491,9 +491,10 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
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/* So devices */
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{IWL_PCI_DEVICE(0x2725, PCI_ANY_ID, iwl_so_trans_cfg)},
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{IWL_PCI_DEVICE(0x2726, PCI_ANY_ID, iwl_snj_trans_cfg)},
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{IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
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{IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
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{IWL_PCI_DEVICE(0x7AF0, PCI_ANY_ID, iwl_so_trans_cfg)},
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{IWL_PCI_DEVICE(0x51F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
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{IWL_PCI_DEVICE(0x51F1, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
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{IWL_PCI_DEVICE(0x54F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
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{IWL_PCI_DEVICE(0x7F70, PCI_ANY_ID, iwl_so_trans_cfg)},
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