dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml
Convert cadence-nand-controller.txt to yaml format. Update cadence-nand-controller.txt to cdns,hp-nfc.yaml in MAINTAINER file. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Niravkumar L Rabara
Miquel Raynal
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1f05f823a1
3 changed files with 76 additions and 54 deletions
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* Cadence NAND controller
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Required properties:
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- compatible : "cdns,hp-nfc"
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- reg : Contains two entries, each of which is a tuple consisting of a
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physical address and length. The first entry is the address and
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length of the controller register set. The second entry is the
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address and length of the Slave DMA data port.
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- reg-names: should contain "reg" and "sdma"
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- #address-cells: should be 1. The cell encodes the chip select connection.
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- #size-cells : should be 0.
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- interrupts : The interrupt number.
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- clocks: phandle of the controller core clock (nf_clk).
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Optional properties:
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- dmas: shall reference DMA channel associated to the NAND controller
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- cdns,board-delay-ps : Estimated Board delay. The value includes the total
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round trip delay for the signals and is used for deciding on values
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associated with data read capture. The example formula for SDR mode is
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the following:
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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+ DQ PAD delay
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Child nodes represent the available NAND chips.
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Required properties of NAND chips:
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- reg: shall contain the native Chip Select ids from 0 to max supported by
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the cadence nand flash controller
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See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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generic bindings.
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Example:
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nand_controller: nand-controller@60000000 {
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compatible = "cdns,hp-nfc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
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reg-names = "reg", "sdma";
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clocks = <&nf_clk>;
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cdns,board-delay-ps = <4830>;
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interrupts = <2 0>;
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nand@0 {
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reg = <0>;
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label = "nand-1";
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};
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nand@1 {
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reg = <1>;
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label = "nand-2";
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};
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};
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75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
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75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
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@ -0,0 +1,75 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence NAND controller
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maintainers:
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- Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
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allOf:
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- $ref: nand-controller.yaml
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properties:
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compatible:
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items:
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- const: cdns,hp-nfc
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reg:
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items:
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- description: Controller register set
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- description: Slave DMA data port register set
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reg-names:
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items:
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- const: reg
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- const: sdma
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 1
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cdns,board-delay-ps:
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description: |
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Estimated Board delay. The value includes the total round trip
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delay for the signals and is used for deciding on values associated
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with data read capture. The example formula for SDR mode is the
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following.
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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+ DQ PAD delay
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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nand-controller@10b80000 {
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compatible = "cdns,hp-nfc";
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reg = <0x10b80000 0x10000>,
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<0x10840000 0x10000>;
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reg-names = "reg", "sdma";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&nf_clk>;
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cdns,board-delay-ps = <4830>;
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nand@0 {
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reg = <0>;
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};
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};
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@ -5009,7 +5009,7 @@ F: drivers/media/platform/cadence/cdns-csi2*
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CADENCE NAND DRIVER
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L: linux-mtd@lists.infradead.org
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S: Orphan
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F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
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F: Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
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F: drivers/mtd/nand/raw/cadence-nand-controller.c
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CADENCE USB3 DRD IP DRIVER
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