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serial: tegra: check for FIFO mode enabled status

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Chips prior to Tegra186 needed delay of 3 UART clock cycles to avoid
data loss. This issue is fixed in Tegra186 and a new flag is added to
check if FIFO mode is enabled. chip data updated to check if this flag
is available for a chip. Tegra186 has new compatible to enable this
flag.

Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/1567572187-29820-7-git-send-email-kyarlagadda@nvidia.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Krishna Yarlagadda 2019-09-04 10:13:01 +05:30 • committed by Greg Kroah-Hartman
parent c9fd37f926
commit 222dcdff34
1 changed files with 46 additions and 6 deletions
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46
drivers/tty/serial/serial-tegra.c
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@ -72,6 +72,8 @@
#define TEGRA_TX_PIO 1 #define TEGRA_TX_PIO 1
#define TEGRA_TX_DMA 2 #define TEGRA_TX_DMA 2
#define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
/** /**
* tegra_uart_chip_data: SOC specific data. * tegra_uart_chip_data: SOC specific data.
* *
@ -84,6 +86,7 @@ struct tegra_uart_chip_data {
bool tx_fifo_full_status; bool tx_fifo_full_status;
bool allow_txfifo_reset_fifo_mode; bool allow_txfifo_reset_fifo_mode;
bool support_clk_src_div; bool support_clk_src_div;
bool fifo_mode_enable_status;
}; };
struct tegra_uart_port { struct tegra_uart_port {
@ -263,6 +266,21 @@ static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
tup->current_baud)); tup->current_baud));
} }
static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
{
unsigned long iir;
unsigned int tmout = 100;
do {
iir = tegra_uart_read(tup, UART_IIR);
if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
return 0;
udelay(1);
} while (--tmout);
return -ETIMEDOUT;
}
static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
{ {
unsigned long fcr = tup->fcr_shadow; unsigned long fcr = tup->fcr_shadow;
@ -282,6 +300,8 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_write(tup, fcr, UART_FCR);
fcr |= UART_FCR_ENABLE_FIFO; fcr |= UART_FCR_ENABLE_FIFO;
tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_write(tup, fcr, UART_FCR);
if (tup->cdata->fifo_mode_enable_status)
tegra_uart_wait_fifo_mode_enabled(tup);
} }
/* Dummy read to ensure the write is posted */ /* Dummy read to ensure the write is posted */
@ -917,12 +937,20 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
/* Dummy read to ensure the write is posted */ /* Dummy read to ensure the write is posted */
tegra_uart_read(tup, UART_SCR); tegra_uart_read(tup, UART_SCR);
if (tup->cdata->fifo_mode_enable_status) {
ret = tegra_uart_wait_fifo_mode_enabled(tup);
dev_err(tup->uport.dev, "FIFO mode not enabled\n");
if (ret < 0)
return ret;
} else {
/* /*
* For all tegra devices (up to t210), there is a hardware issue that * For all tegra devices (up to t210), there is a hardware
* requires software to wait for 3 UART clock periods after enabling * issue that requires software to wait for 3 UART clock
* the TX fifo, otherwise data could be lost. * periods after enabling the TX fifo, otherwise data could
* be lost.
*/ */
tegra_uart_wait_cycle_time(tup, 3); tegra_uart_wait_cycle_time(tup, 3);
}
/* /*
* Initialize the UART with default configuration * Initialize the UART with default configuration
@ -1293,12 +1321,21 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data = {
.tx_fifo_full_status = false, .tx_fifo_full_status = false,
.allow_txfifo_reset_fifo_mode = true, .allow_txfifo_reset_fifo_mode = true,
.support_clk_src_div = false, .support_clk_src_div = false,
.fifo_mode_enable_status = false,
}; };
static struct tegra_uart_chip_data tegra30_uart_chip_data = { static struct tegra_uart_chip_data tegra30_uart_chip_data = {
.tx_fifo_full_status = true, .tx_fifo_full_status = true,
.allow_txfifo_reset_fifo_mode = false, .allow_txfifo_reset_fifo_mode = false,
.support_clk_src_div = true, .support_clk_src_div = true,
.fifo_mode_enable_status = false,
};
static struct tegra_uart_chip_data tegra186_uart_chip_data = {
.tx_fifo_full_status = true,
.allow_txfifo_reset_fifo_mode = false,
.support_clk_src_div = true,
.fifo_mode_enable_status = true,
}; };
static const struct of_device_id tegra_uart_of_match[] = { static const struct of_device_id tegra_uart_of_match[] = {
@ -1308,6 +1345,9 @@ static const struct of_device_id tegra_uart_of_match[] = {
}, { }, {
.compatible = "nvidia,tegra20-hsuart", .compatible = "nvidia,tegra20-hsuart",
.data = &tegra20_uart_chip_data, .data = &tegra20_uart_chip_data,
}, {
.compatible = "nvidia,tegra186-hsuart",
.data = &tegra186_uart_chip_data,
}, { }, {
}, },
}; };