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drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA

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Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled.

v2: Fix typo in commit message (Animesh)

Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-7-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2023-04-28 12:54:26 +03:00 • committed by Radhakrishna Sripada
parent ac50317e26
commit 237e7be0bf
1 changed files with 5 additions and 2 deletions
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7
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@ -2349,8 +2349,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
/* TODO: HDMI FRL */
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
/* DP2.0 10G and 20G rates enable MPLLA*/
if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
else
val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |