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drm/amd/display: Clean FPGA code in dc

Browse source 
[Why]
Drop dead code for Linux.

[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Qingqing Zhuo 2023-03-16 09:05:58 -04:00 • committed by Alex Deucher
parent 7e60ab4eb3
commit 25879d7b49
63 changed files with 811 additions and 1333 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
View file

@ -111,13 +111,11 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
bp->funcs->set_dce_clock(bp, &dce_clk_params);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
dmcu->funcs->set_psr_wait_loop(dmcu,
actual_clock / 1000 / 7);
}
}
clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
return actual_clock;
@ -153,13 +151,11 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
dmcu->funcs->set_psr_wait_loop(dmcu,
actual_clock / 1000 / 7);
}
}
clk_mgr->dfs_bypass_disp_clk = actual_clock;
return actual_clock;

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
View file

@ -135,13 +135,11 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di
VBIOSSMC_MSG_SetDispclkFreq,
khz_to_mhz_ceil(requested_dispclk_khz));
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
dmcu->funcs->set_psr_wait_loop(dmcu,
actual_dispclk_set_mhz / 7);
}
}
return actual_dispclk_set_mhz * 1000;
}

20
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
View file

@ -531,6 +531,11 @@ void dcn20_clk_mgr_construct(
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
int dprefclk_did;
int target_div;
uint32_t pll_req_reg;
struct fixed31_32 pll_req;
clk_mgr->base.ctx = ctx;
clk_mgr->pp_smu = pp_smu;
clk_mgr->base.funcs = &dcn2_funcs;
@ -547,19 +552,12 @@ void dcn20_clk_mgr_construct(
clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
clk_mgr->base.dentist_vco_freq_khz = 3850000;
} else {
/* DFS Slice 2 should be used for DPREFCLK */
int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
/* Convert DPREFCLK DFS Slice DID to actual divider */
int target_div = dentist_get_divider_from_did(dprefclk_did);
target_div = dentist_get_divider_from_did(dprefclk_did);
/* get FbMult value */
uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
struct fixed31_32 pll_req;
pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
/* set up a fixed-point number
* this works because the int part is on the right edge of the register
@ -582,7 +580,6 @@ void dcn20_clk_mgr_construct(
/* Calculate the DPREFCLK in kHz.*/
clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
}
//Integrated_info table does not exist on dGPU projects so should not be referenced
//anywhere in code for dGPUs.
//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
@ -590,4 +587,3 @@ void dcn20_clk_mgr_construct(
dce_clock_read_ss_info(clk_mgr);
}

6
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
View file

@ -190,11 +190,6 @@ void dcn201_clk_mgr_construct(struct dc_context *ctx,
clk_mgr->dprefclk_ss_divider = 1000;
clk_mgr->ss_on_dprefclk = false;
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dcn201_funcs.update_clocks = dcn2_update_clocks_fpga;
clk_mgr->base.dprefclk_khz = 600000;
clk_mgr->base.dentist_vco_freq_khz = 3000000;
} else {
clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);
clk_mgr->base.dprefclk_khz *= 100;
@ -206,7 +201,6 @@ void dcn201_clk_mgr_construct(struct dc_context *ctx,
if (clk_mgr->base.dentist_vco_freq_khz == 0)
clk_mgr->base.dentist_vco_freq_khz = 3000000;
}
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)

11
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View file

@ -705,6 +705,7 @@ void rn_clk_mgr_construct(
struct dpm_clocks clock_table = { 0 };
enum pp_smu_status status = 0;
int is_green_sardine = 0;
struct clk_log_info log_info = {0};
#if defined(CONFIG_DRM_AMD_DC_FP)
is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
@ -725,12 +726,6 @@ void rn_clk_mgr_construct(
clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
clk_mgr->base.dentist_vco_freq_khz = 3600000;
} else {
struct clk_log_info log_info = {0};
clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
/* SMU Version 55.51.0 and up no longer have an issue
@ -766,7 +761,6 @@ void rn_clk_mgr_construct(
}
/* Saved clocks configured at boot for debug purposes */
rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
}
clk_mgr->base.dprefclk_khz = 600000;
dce_clock_read_ss_info(clk_mgr);
@ -786,9 +780,8 @@ void rn_clk_mgr_construct(
}
}
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
/* enable powerfeatures when displaycount goes to 0 */
if (clk_mgr->smu_ver >= 0x00371500)
rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
}
}

5
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
View file

@ -147,16 +147,13 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
VBIOSSMC_MSG_SetDispclkFreq,
khz_to_mhz_ceil(requested_dispclk_khz));
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
dmcu->funcs->set_psr_wait_loop(dmcu,
actual_dispclk_set_mhz / 7);
}
}
// pmfw always set clock more than or equal requested clock
if (!IS_DIAG_DC(dc->ctx->dce_environment))
ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz));
return actual_dispclk_set_mhz * 1000;
@ -221,14 +218,12 @@ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phy
int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
{
int actual_dppclk_set_mhz = -1;
struct dc *dc = clk_mgr->base.ctx->dc;
actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
khz_to_mhz_ceil(requested_dpp_khz));
if (!IS_DIAG_DC(dc->ctx->dce_environment))
ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));
return actual_dppclk_set_mhz * 1000;

10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
View file

@ -521,6 +521,8 @@ void dcn3_clk_mgr_construct(
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
struct clk_state_registers_and_bypass s = { 0 };
clk_mgr->base.ctx = ctx;
clk_mgr->base.funcs = &dcn3_funcs;
clk_mgr->regs = &clk_mgr_regs;
@ -537,13 +539,6 @@ void dcn3_clk_mgr_construct(
clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.funcs = &dcn3_fpga_funcs;
clk_mgr->base.dentist_vco_freq_khz = 3650000;
} else {
struct clk_state_registers_and_bypass s = { 0 };
/* integer part is now VCO frequency in kHz */
clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
@ -557,7 +552,6 @@ void dcn3_clk_mgr_construct(
//ASSERT(s.dprefclk != 0);
if (s.dprefclk != 0)
clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
}
clk_mgr->dfs_bypass_enabled = false;

18
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
View file

@ -117,7 +117,7 @@ static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
display_count = vg_get_active_display_cnt_wa(dc, context);
/* if we can go lower, go lower */
if (display_count == 0 && !IS_DIAG_DC(dc->ctx->dce_environment)) {
if (display_count == 0) {
union display_idle_optimization_u idle_info = { 0 };
idle_info.idle_info.df_request_disabled = 1;
@ -151,10 +151,8 @@ static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < 100000)
new_clocks->dppclk_khz = 100000;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@ -664,6 +662,7 @@ void vg_clk_mgr_construct(
struct dccg *dccg)
{
struct smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_log_info log_info = {0};
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &vg_funcs;
@ -703,12 +702,6 @@ void vg_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
vg_funcs.update_clocks = dcn2_update_clocks_fpga;
clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver)
@ -728,7 +721,6 @@ void vg_clk_mgr_construct(
}
/* Saved clocks configured at boot for debug purposes */
vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
dce_clock_read_ss_info(&clk_mgr->base);
@ -746,12 +738,6 @@ void vg_clk_mgr_construct(
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
smu_dpm_clks.dpm_clks);
/*
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->base.smu_ver) {
enable powerfeatures when displaycount goes to 0
dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
}
*/
}
void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View file

@ -205,10 +205,8 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < 100000)
new_clocks->dppclk_khz = 100000;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@ -672,6 +670,7 @@ void dcn31_clk_mgr_construct(
struct dccg *dccg)
{
struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_log_info log_info = {0};
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn31_funcs;
@ -711,11 +710,6 @@ void dcn31_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver)
@ -733,8 +727,6 @@ void dcn31_clk_mgr_construct(
dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
dce_clock_read_ss_info(&clk_mgr->base);

10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
View file

@ -241,10 +241,8 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < 100000)
new_clocks->dppclk_khz = 100000;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@ -724,6 +722,7 @@ void dcn314_clk_mgr_construct(
struct dccg *dccg)
{
struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_log_info log_info = {0};
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn314_funcs;
@ -763,11 +762,6 @@ void dcn314_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver)
@ -785,8 +779,6 @@ void dcn314_clk_mgr_construct(
dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
dce_clock_read_ss_info(&clk_mgr->base);

10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
View file

@ -184,12 +184,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@ -600,6 +598,7 @@ void dcn315_clk_mgr_construct(
struct dccg *dccg)
{
struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_log_info log_info = {0};
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn315_funcs;
@ -639,11 +638,6 @@ void dcn315_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver > 0)
@ -658,8 +652,6 @@ void dcn315_clk_mgr_construct(
dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

11
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View file

@ -207,12 +207,10 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < 100000)
new_clocks->dppclk_khz = 100000;
if (new_clocks->dispclk_khz < 100000)
new_clocks->dispclk_khz = 100000;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@ -616,6 +614,7 @@ void dcn316_clk_mgr_construct(
struct dccg *dccg)
{
struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_log_info log_info = {0};
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn316_funcs;
@ -655,12 +654,6 @@ void dcn316_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver > 0)
@ -683,8 +676,6 @@ void dcn316_clk_mgr_construct(
dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
View file

@ -941,7 +941,6 @@ void dcn32_clk_mgr_construct(
clk_mgr->base.clks.ref_dtbclk_khz = 268750;
}
/* integer part is now VCO frequency in kHz */
clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);

2
drivers/gpu/drm/amd/display/dc/core/dc.c
View file

@ -3588,7 +3588,6 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
/*set logical flag for lock/unlock use*/
@ -3611,7 +3610,6 @@ static void commit_planes_for_stream(struct dc *dc,
plane_state->flip_immediate = false;
}
}
}
// Update Type FULL, Surface updates
for (j = 0; j < dc->res_pool->pipe_count; j++) {

30
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View file

@ -490,25 +490,6 @@ bool dc_stream_add_writeback(struct dc *dc,
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb->otg_inst = stream_status->primary_otg_inst;
}
if (IS_DIAG_DC(dc->ctx->dce_environment)) {
if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dm_error("DC: update_bandwidth failed!\n");
return false;
}
/* enable writeback */
if (dc->hwss.enable_writeback) {
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
if (dwb->funcs->is_enabled(dwb)) {
/* writeback pipe already enabled, only need to update */
dc->hwss.update_writeback(dc, wb_info, dc->current_state);
} else {
/* Enable writeback pipe from scratch*/
dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
}
}
}
return true;
}
@ -553,17 +534,6 @@ bool dc_stream_remove_writeback(struct dc *dc,
}
stream->num_wb_info = j;
if (IS_DIAG_DC(dc->ctx->dce_environment)) {
/* recalculate and apply DML parameters */
if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dm_error("DC: update_bandwidth failed!\n");
return false;
}
/* disable writeback */
if (dc->hwss.disable_writeback)
dc->hwss.disable_writeback(dc, dwb_pipe_inst);
}
return true;
}

4
drivers/gpu/drm/amd/display/dc/dc_helper.c
View file

@ -464,8 +464,7 @@ void generic_reg_wait(const struct dc_context *ctx,
field_value = get_reg_field_value_ex(reg_val, mask, shift);
if (field_value == condition_value) {
if (i * delay_between_poll_us > 1000 &&
!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
if (i * delay_between_poll_us > 1000)
DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n",
delay_between_poll_us * i / 1000,
func_name, line);
@ -477,7 +476,6 @@ void generic_reg_wait(const struct dc_context *ctx,
delay_between_poll_us, time_out_num_tries,
func_name, line);
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
BREAK_TO_DEBUGGER();
}

7
drivers/gpu/drm/amd/display/dc/dc_types.h
View file

@ -69,13 +69,6 @@ enum dce_environment {
DCE_ENV_VIRTUAL_HW
};
/* Note: use these macro definitions instead of direct comparison! */
#define IS_FPGA_MAXIMUS_DC(dce_environment) \
(dce_environment == DCE_ENV_FPGA_MAXIMUS)
#define IS_DIAG_DC(dce_environment) \
(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
struct dc_perf_trace {
unsigned long read_count;
unsigned long write_count;

38
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View file

@ -920,25 +920,6 @@ static bool dce112_program_pix_clk(
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0};
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
unsigned dp_dto_ref_100hz = 7000000;
unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
/* Set DTO values: phase = target clock, modulo = reference clock */
REG_WRITE(PHASE[inst], clock_100hz);
REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
/* Enable DTO */
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1,
PIPE0_DTO_SRC_SEL, 1);
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
return true;
}
/* First disable SS
* ATOMBIOS will enable by default SS on PLL for DP,
* do not disable it here
@ -1015,25 +996,6 @@ static bool dcn31_program_pix_clk(
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
} else {
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
unsigned dp_dto_ref_100hz = 7000000;
unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
/* Set DTO values: phase = target clock, modulo = reference clock */
REG_WRITE(PHASE[inst], clock_100hz);
REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
/* Enable DTO */
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1,
PIPE0_DTO_SRC_SEL, 1);
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
return true;
}
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE(PIXEL_RATE_CNTL[inst],

2
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
View file

@ -1093,12 +1093,10 @@ static void dcn21_dmcu_construct(
dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
dmcu_dce->base.psp_version = psp_version;
}
}
struct dmcu *dce_dmcu_create(
struct dc_context *ctx,

3
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file

@ -209,9 +209,6 @@ static bool dce110_enable_display_power_gating(
struct dc_context *ctx = dc->ctx;
unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
return true;
if (power_gating == PIPE_GATING_CONTROL_INIT)
cntl = ASIC_PIPE_INIT;
else if (power_gating == PIPE_GATING_CONTROL_ENABLE)

3
drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
View file

@ -120,9 +120,6 @@ static bool dce112_enable_display_power_gating(
enum bp_pipe_control_action cntl;
struct dc_context *ctx = dc->ctx;
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
return true;
if (power_gating == PIPE_GATING_CONTROL_INIT)
cntl = ASIC_PIPE_INIT;
else if (power_gating == PIPE_GATING_CONTROL_ENABLE)

3
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
View file

@ -159,9 +159,6 @@ static bool dce120_enable_display_power_gating(
enum bp_pipe_control_action cntl;
struct dc_context *ctx = dc->ctx;
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
return true;
if (power_gating == PIPE_GATING_CONTROL_INIT)
cntl = ASIC_PIPE_INIT;
else if (power_gating == PIPE_GATING_CONTROL_ENABLE)

30
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View file

@ -1012,7 +1012,6 @@ static void dcn10_reset_back_end_for_pipe(
return;
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
link = pipe_ctx->stream->link;
/* DPMS may already disable or */
/* dpms_off status is incorrect due to fastboot
@ -1038,7 +1037,6 @@ static void dcn10_reset_back_end_for_pipe(
pipe_ctx->stream_res.audio = NULL;
}
}
}
/* by upper caller loop, parent pipe: pipe0, will be reset last.
* back end share by all pipes and will be disable only when disable
@ -1499,28 +1497,6 @@ void dcn10_init_hw(struct dc *dc)
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
REG_WRITE(REFCLK_CNTL, 0);
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
//Enable ability to power gate / don't force power on permanently
if (hws->funcs.enable_power_gating_plane)
hws->funcs.enable_power_gating_plane(hws, true);
return;
}
if (!dcb->funcs->is_accelerated_mode(dcb))
hws->funcs.disable_vga(dc->hwseq);
@ -1532,7 +1508,6 @@ void dcn10_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (res_pool->dccg && res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
@ -1549,7 +1524,6 @@ void dcn10_init_hw(struct dc *dc)
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
}
}
} else
ASSERT_CRITICAL(false);
@ -3070,7 +3044,6 @@ void dcn10_prepare_bandwidth(
if (dc->debug.sanity_checks)
hws->funcs.verify_allow_pstate_change_high(dc);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (context->stream_count == 0)
context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
@ -3078,7 +3051,6 @@ void dcn10_prepare_bandwidth(
dc->clk_mgr,
context,
false);
}
dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
&context->bw_ctx.bw.dcn.watermarks,
@ -3110,7 +3082,6 @@ void dcn10_optimize_bandwidth(
if (dc->debug.sanity_checks)
hws->funcs.verify_allow_pstate_change_high(dc);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (context->stream_count == 0)
context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
@ -3118,7 +3089,6 @@ void dcn10_optimize_bandwidth(
dc->clk_mgr,
context,
true);
}
hubbub->funcs->program_watermarks(hubbub,
&context->bw_ctx.bw.dcn.watermarks,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View file

@ -653,8 +653,6 @@ void optc1_lock(struct timing_generator *optc)
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
/* Should be fast, status does not update on maximus */
if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
1, 10);

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file

@ -1651,8 +1651,7 @@ static bool dcn10_resource_construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto fail;
dcn10_hw_sequencer_construct(dc);

5
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View file

@ -2480,7 +2480,6 @@ static void dcn20_reset_back_end_for_pipe(
return;
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
/* DPMS may already disable or */
/* dpms_off status is incorrect due to fastboot
* feature. When system resume from S4 with second
@ -2506,10 +2505,6 @@ static void dcn20_reset_back_end_for_pipe(
pipe_ctx->stream_res.audio = NULL;
}
}
}
else if (pipe_ctx->stream_res.dsc) {
dc->link_srv->set_dsc_enable(pipe_ctx, false);
}
/* by upper caller loop, parent pipe: pipe0, will be reset last.
* back end share by all pipes and will be disable only when disable

4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
View file

@ -145,8 +145,4 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
dc->hwss = dcn20_funcs;
dc->hwseq->funcs = dcn20_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
View file

@ -391,7 +391,6 @@ void optc2_triplebuffer_lock(struct timing_generator *optc)
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
1, 10);

13
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View file

@ -2488,15 +2488,9 @@ static bool dcn20_resource_construct(
dc->caps.dp_hdmi21_pcon_support = true;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
pool->base.pipe_count = 4;
pool->base.mpcc_count = pool->base.pipe_count;
dc->debug = debug_defaults_diags;
} else {
dc->debug = debug_defaults_diags;
}
//dcn2.0x
dc->work_arounds.dedcn20_305_wa = true;
@ -2734,8 +2728,7 @@ static bool dcn20_resource_construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
dcn20_hw_sequencer_construct(dc);

17
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
View file

@ -231,23 +231,12 @@ void dcn201_init_hw(struct dc *dc)
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
hws->funcs.dccg_init(hws);
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_WRITE(REFCLK_CNTL, 0);
} else {
hws->funcs.bios_golden_init(dc);
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (res_pool->dccg && res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
@ -262,7 +251,6 @@ void dcn201_init_hw(struct dc *dc)
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
}
}
} else
ASSERT_CRITICAL(false);
for (i = 0; i < dc->link_count; i++) {
@ -276,7 +264,6 @@ void dcn201_init_hw(struct dc *dc)
}
if (hws->fb_offset.quad_part == 0)
read_mmhub_vm_setup(hws);
}
/* Blank pixel data with OPP DPG */
for (i = 0; i < res_pool->timing_generator_count; i++) {
@ -362,10 +349,6 @@ void dcn201_init_hw(struct dc *dc)
tg->funcs->tg_init(tg);
}
/* end of FPGA. Below if real ASIC */
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
return;
for (i = 0; i < res_pool->audio_count; i++) {
struct audio *audio = res_pool->audios[i];

1
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c
View file

@ -55,7 +55,6 @@ static void optc201_triplebuffer_lock(struct timing_generator *optc)
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
1, 10);

3
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
View file

@ -1272,8 +1272,7 @@ static bool dcn201_resource_construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
dcn201_hw_sequencer_construct(dc);

4
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
View file

@ -151,8 +151,4 @@ void dcn21_hw_sequencer_construct(struct dc *dc)
dc->hwss = dcn21_funcs;
dc->hwseq->funcs = dcn21_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

8
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
View file

@ -1503,11 +1503,6 @@ static bool dcn21_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
pool->base.pipe_count = 4;
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
@ -1721,8 +1716,7 @@ static bool dcn21_resource_construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
dcn21_hw_sequencer_construct(dc);

28
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View file

@ -330,10 +330,6 @@ void dcn30_enable_writeback(
DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
__func__, wb_info->dwb_pipe_inst,\
wb_info->mpcc_inst);
if (IS_DIAG_DC(dc->ctx->dce_environment)) {
/*till diags switch to warmup interface*/
dcn30_mmhubbub_warmup(dc, 1, wb_info);
}
/* Update writeback pipe */
dcn30_set_writeback(dc, wb_info, context);
@ -447,28 +443,6 @@ void dcn30_init_hw(struct dc *dc)
if (res_pool->dccg->funcs->dccg_init)
res_pool->dccg->funcs->dccg_init(res_pool->dccg);
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
REG_WRITE(REFCLK_CNTL, 0);
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
//Enable ability to power gate / don't force power on permanently
if (hws->funcs.enable_power_gating_plane)
hws->funcs.enable_power_gating_plane(hws, true);
return;
}
if (!dcb->funcs->is_accelerated_mode(dcb)) {
hws->funcs.bios_golden_init(dc);
hws->funcs.disable_vga(dc->hwseq);
@ -491,7 +465,6 @@ void dcn30_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (res_pool->dccg && res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
@ -508,7 +481,6 @@ void dcn30_init_hw(struct dc *dc)
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
}
}
} else
ASSERT_CRITICAL(false);

4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
View file

@ -151,8 +151,4 @@ void dcn30_hw_sequencer_construct(struct dc *dc)
dc->hwss = dcn30_funcs;
dc->hwseq->funcs = dcn30_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
View file

@ -55,7 +55,6 @@ void optc3_triplebuffer_lock(struct timing_generator *optc)
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
1, 10);

8
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View file

@ -2376,10 +2376,7 @@ static bool dcn30_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -2577,8 +2574,7 @@ static bool dcn30_resource_construct(
/* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

8
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
View file

@ -1513,10 +1513,7 @@ static bool dcn301_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -1710,8 +1707,7 @@ static bool dcn301_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

5
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
View file

@ -1309,8 +1309,6 @@ static bool dcn302_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
@ -1489,8 +1487,7 @@ static bool dcn302_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, pool,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

5
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
View file

@ -1232,8 +1232,6 @@ static bool dcn303_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
@ -1400,8 +1398,7 @@ static bool dcn303_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, pool,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

28
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
View file

@ -117,28 +117,6 @@ void dcn31_init_hw(struct dc *dc)
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
REG_WRITE(REFCLK_CNTL, 0);
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
//Enable ability to power gate / don't force power on permanently
if (hws->funcs.enable_power_gating_plane)
hws->funcs.enable_power_gating_plane(hws, true);
return;
}
if (!dcb->funcs->is_accelerated_mode(dcb)) {
hws->funcs.bios_golden_init(dc);
if (hws->funcs.disable_vga)
@ -154,7 +132,6 @@ void dcn31_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (res_pool->dccg && res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
@ -171,7 +148,6 @@ void dcn31_init_hw(struct dc *dc)
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
}
}
} else
ASSERT_CRITICAL(false);
@ -553,7 +529,6 @@ static void dcn31_reset_back_end_for_pipe(
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, NULL);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
link = pipe_ctx->stream->link;
/* DPMS may already disable or */
/* dpms_off status is incorrect due to fastboot
@ -580,9 +555,6 @@ static void dcn31_reset_back_end_for_pipe(
pipe_ctx->stream_res.audio = NULL;
}
}
} else if (pipe_ctx->stream_res.dsc) {
dc->link_srv->set_dsc_enable(pipe_ctx, false);
}
pipe_ctx->stream = NULL;
DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",

4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
View file

@ -154,8 +154,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc)
dc->hwss = dcn31_funcs;
dc->hwseq->funcs = dcn31_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

15
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View file

@ -1341,13 +1341,6 @@ static struct dce_hwseq *dcn31_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
/* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling
* function core_link_enable_stream
*/
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
hws->wa.dp_hpo_and_otg_sequence = true;
}
return hws;
}
@ -1988,10 +1981,7 @@ static bool dcn31_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -2195,8 +2185,7 @@ static bool dcn31_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

4
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
View file

@ -160,8 +160,4 @@ void dcn314_hw_sequencer_construct(struct dc *dc)
dc->hwss = dcn314_funcs;
dc->hwseq->funcs = dcn314_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

10
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
View file

@ -1375,13 +1375,6 @@ static struct dce_hwseq *dcn314_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
/* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling
* function core_link_enable_stream
*/
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
hws->wa.dp_hpo_and_otg_sequence = true;
}
return hws;
}
@ -2101,8 +2094,7 @@ static bool dcn314_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

15
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
View file

@ -1342,13 +1342,6 @@ static struct dce_hwseq *dcn31_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
/* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling
* function core_link_enable_stream
*/
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
hws->wa.dp_hpo_and_otg_sequence = true;
}
return hws;
}
@ -1947,10 +1940,7 @@ static bool dcn315_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -2131,8 +2121,7 @@ static bool dcn315_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

15
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
View file

@ -1340,13 +1340,6 @@ static struct dce_hwseq *dcn31_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
/* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling
* function core_link_enable_stream
*/
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
hws->wa.dp_hpo_and_otg_sequence = true;
}
return hws;
}
@ -1844,10 +1837,7 @@ static bool dcn316_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -2028,8 +2018,7 @@ static bool dcn316_resource_construct(
/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer and Plane caps */

4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
View file

@ -161,8 +161,4 @@ void dcn32_hw_sequencer_init_functions(struct dc *dc)
dc->hwss = dcn32_funcs;
dc->hwseq->funcs = dcn32_private_funcs;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc->hwss.init_hw = dcn20_fpga_init_hw;
dc->hwseq->funcs.init_pipes = NULL;
}
}

9
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View file

@ -2260,10 +2260,7 @@ static bool dcn32_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -2319,7 +2316,6 @@ static bool dcn32_resource_construct(
}
/* DML */
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
/* IRQ Service */
@ -2457,8 +2453,7 @@ static bool dcn32_resource_construct(
/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer init functions and Plane caps */

9
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
View file

@ -1801,10 +1801,7 @@ static bool dcn321_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc->debug = debug_defaults_diags;
} else
dc->debug = debug_defaults_diags;
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
@ -1860,7 +1857,6 @@ static bool dcn321_resource_construct(
}
/* DML */
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
/* IRQ Service */
@ -1993,8 +1989,7 @@ static bool dcn321_resource_construct(
/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
&res_create_funcs))
goto create_fail;
/* HW Sequencer init functions and Plane caps */

2
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
View file

@ -333,7 +333,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
memcpy(s, dcn3_01_soc.clock_limits, sizeof(dcn3_01_soc.clock_limits));
/* Default clock levels are used for diags, which may lead to overclocking. */
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
dcn3_01_soc.num_chans = bw_params->num_channels;
@ -372,7 +371,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
}
}
memcpy(dcn3_01_soc.clock_limits, s, sizeof(dcn3_01_soc.clock_limits));

17
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
View file

@ -582,6 +582,7 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
@ -589,9 +590,6 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits));
// Default clock levels are used for diags, which may lead to overclocking.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
dcn3_1_soc.num_chans = bw_params->num_channels;
@ -642,7 +640,6 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
if (clk_table->num_entries) {
dcn3_1_soc.num_states = clk_table->num_entries;
}
}
memcpy(dcn3_1_soc.clock_limits, s, sizeof(dcn3_1_soc.clock_limits));
@ -655,10 +652,7 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
else
dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
}
void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
@ -719,10 +713,7 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN315);
else
dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA);
}
void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
@ -738,8 +729,6 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
memcpy(s, dcn3_16_soc.clock_limits, sizeof(dcn3_16_soc.clock_limits));
// Default clock levels are used for diags, which may lead to overclocking.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;
dcn3_16_soc.num_chans = bw_params->num_channels;
@ -803,7 +792,6 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
if (clk_table->num_entries) {
dcn3_16_soc.num_states = clk_table->num_entries;
}
}
memcpy(dcn3_16_soc.clock_limits, s, sizeof(dcn3_16_soc.clock_limits));
@ -817,10 +805,7 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);
else
dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA);
}
int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc)

8
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
View file

@ -1432,14 +1432,6 @@ static void dml_rq_dlg_get_dlg_params(
dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
// hack for FPGA
if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
}
}
disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

6
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
View file

@ -190,8 +190,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
dc_assert_fp_enabled();
// Default clock levels are used for diags, which may lead to overclocking.
if (!IS_DIAG_DC(dc->ctx->dce_environment) && dc->config.use_default_clock_table == false) {
if (dc->config.use_default_clock_table == false) {
dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
@ -267,10 +266,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
dcn20_patch_bounding_box(dc, &dcn3_14_soc);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);
else
dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);
}
static bool is_dual_plane(enum surface_pixel_format format)

8
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
View file

@ -1520,14 +1520,6 @@ static void dml_rq_dlg_get_dlg_params(
dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
// hack for FPGA
if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
}
}
disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

4
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View file

@ -2530,7 +2530,6 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
{
dc_assert_fp_enabled();
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
/* Overrides from dc->config options */
dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
@ -2602,7 +2601,6 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
}
/* DML DSC delay factor workaround */
dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
@ -2614,7 +2612,7 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
if (bw_params->clk_table.entries[0].memclk_mhz) {
if (dc->debug.use_legacy_soc_bb_mechanism) {
unsigned int i = 0, j = 0, num_states = 0;

4
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
View file

@ -471,7 +471,6 @@ static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
{
dc_assert_fp_enabled();
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
/* Overrides from dc->config options */
dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
@ -543,7 +542,6 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
}
/* DML DSC delay factor workaround */
dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
@ -555,7 +553,6 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
if (dc->debug.use_legacy_soc_bb_mechanism) {
unsigned int i = 0, j = 0, num_states = 0;
@ -700,5 +697,4 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
if (dc->current_state)
dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
}
}

1
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
View file

@ -113,7 +113,6 @@ void dml_init_instance(struct display_mode_lib *lib,
lib->funcs = dml30_funcs;
break;
case DML_PROJECT_DCN31:
case DML_PROJECT_DCN31_FPGA:
case DML_PROJECT_DCN315:
lib->funcs = dml31_funcs;
break;

1
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
View file

@ -41,7 +41,6 @@ enum dml_project {
DML_PROJECT_DCN30,
DML_PROJECT_DCN31,
DML_PROJECT_DCN315,
DML_PROJECT_DCN31_FPGA,
DML_PROJECT_DCN314,
DML_PROJECT_DCN32,
};

73
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
View file

@ -28,24 +28,6 @@
#include "dccg.h"
#include "clk_mgr.h"
static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
{
switch (link->link_enc->transmitter) {
case TRANSMITTER_UNIPHY_A:
return PHYD32CLKA;
case TRANSMITTER_UNIPHY_B:
return PHYD32CLKB;
case TRANSMITTER_UNIPHY_C:
return PHYD32CLKC;
case TRANSMITTER_UNIPHY_D:
return PHYD32CLKD;
case TRANSMITTER_UNIPHY_E:
return PHYD32CLKE;
default:
return PHYD32CLKA;
}
}
static void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
struct fixed31_32 throttled_vcp_size)
{
@ -120,44 +102,12 @@ static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)
DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
}
static void enable_hpo_dp_fpga_link_output(struct dc_link *link,
const struct link_resource *link_res,
enum signal_type signal,
enum clock_source_id clock_source,
const struct dc_link_settings *link_settings)
{
const struct dc *dc = link->dc;
enum phyd32clk_clock_source phyd32clk = get_phyd32clk_src(link);
int phyd32clk_freq_khz = link_settings->link_rate == LINK_RATE_UHBR10 ? 312500 :
link_settings->link_rate == LINK_RATE_UHBR13_5 ? 412875 :
link_settings->link_rate == LINK_RATE_UHBR20 ? 625000 : 0;
dm_set_phyd32clk(dc->ctx, phyd32clk_freq_khz);
dc->res_pool->dccg->funcs->set_physymclk(
dc->res_pool->dccg,
link->link_enc_hw_inst,
PHYSYMCLK_FORCE_SRC_PHYD32CLK,
true);
dc->res_pool->dccg->funcs->enable_symclk32_le(
dc->res_pool->dccg,
link_res->hpo_dp_link_enc->inst,
phyd32clk);
link_res->hpo_dp_link_enc->funcs->link_enable(
link_res->hpo_dp_link_enc,
link_settings->lane_count);
}
static void enable_hpo_dp_link_output(struct dc_link *link,
const struct link_resource *link_res,
enum signal_type signal,
enum clock_source_id clock_source,
const struct dc_link_settings *link_settings)
{
if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment))
enable_hpo_dp_fpga_link_output(link, link_res, signal,
clock_source, link_settings);
else
link_res->hpo_dp_link_enc->funcs->enable_link_phy(
link_res->hpo_dp_link_enc,
link_settings,
@ -165,37 +115,14 @@ static void enable_hpo_dp_link_output(struct dc_link *link,
link->link_enc->hpd_source);
}
static void disable_hpo_dp_fpga_link_output(struct dc_link *link,
const struct link_resource *link_res,
enum signal_type signal)
{
const struct dc *dc = link->dc;
link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
dc->res_pool->dccg->funcs->disable_symclk32_le(
dc->res_pool->dccg,
link_res->hpo_dp_link_enc->inst);
dc->res_pool->dccg->funcs->set_physymclk(
dc->res_pool->dccg,
link->link_enc_hw_inst,
PHYSYMCLK_FORCE_SRC_SYMCLK,
false);
dm_set_phyd32clk(dc->ctx, 0);
}
static void disable_hpo_dp_link_output(struct dc_link *link,
const struct link_resource *link_res,
enum signal_type signal)
{
if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment)) {
disable_hpo_dp_fpga_link_output(link, link_res, signal);
} else {
link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
link_res->hpo_dp_link_enc->funcs->disable_link_phy(
link_res->hpo_dp_link_enc, signal);
}
}
static void set_hpo_dp_link_test_pattern(struct dc_link *link,
const struct link_resource *link_res,

28
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
View file

@ -765,7 +765,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
struct dc_stream_state *stream = pipe_ctx->stream;
bool result = false;
if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
if (dc_is_virtual_signal(stream->signal))
result = true;
else
result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
@ -778,7 +778,6 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
{
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *odm_pipe;
int opp_cnt = 1;
@ -816,8 +815,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
/* Enable DSC in encoder */
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)
&& !dp_is_128b_132b_signal(pipe_ctx)) {
if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) {
DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
dsc_optc_config_log(dsc, &dsc_optc_cfg);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
@ -849,7 +847,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
false,
NULL,
true);
else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
else {
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
pipe_ctx->stream_res.stream_enc,
OPTC_DSC_DISABLED, 0, 0);
@ -2271,8 +2269,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
}
}
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
if (dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
@ -2358,6 +2355,8 @@ void link_set_dpms_on(
enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
bool apply_edp_fast_boot_optimization =
pipe_ctx->stream->apply_edp_fast_boot_optimization;
ASSERT(is_master_pipe_for_link(link, pipe_ctx));
@ -2375,8 +2374,7 @@ void link_set_dpms_on(
}
}
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
if (dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
link_enc = link_enc_cfg_get_link_enc(link);
@ -2402,10 +2400,6 @@ void link_set_dpms_on(
link_hwss->setup_stream_attribute(pipe_ctx);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
bool apply_edp_fast_boot_optimization =
pipe_ctx->stream->apply_edp_fast_boot_optimization;
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
// Enable VPG before building infoframe
@ -2527,14 +2521,6 @@ void link_set_dpms_on(
dc->hwss.enable_audio_stream(pipe_ctx);
} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
if (dp_is_128b_132b_signal(pipe_ctx))
dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx);
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
dc_is_virtual_signal(pipe_ctx->stream->signal))
link_set_dsc_enable(pipe_ctx, true);
}
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
set_avmute(pipe_ctx, false);
}

3
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
View file

@ -326,8 +326,7 @@ bool dp_is_fec_supported(const struct dc_link *link)
return (dc_is_dp_signal(link->connector_signal) && link_enc &&
link_enc->features.fec_supported &&
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
}
bool dp_should_enable_fec(const struct dc_link *link)