dt-bindings: memory: mediatek: Convert SMI to DT schema
Convert MediaTek SMI to DT schema. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201103054200.21386-2-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Yong Wu
Krzysztof Kozlowski
parent
e2bcad676c
commit
27bb0e4285
4 changed files with 270 additions and 100 deletions
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SMI (Smart Multimedia Interface) Common
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Mediatek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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for generation 1, the register is at smi ao base(smi always on register
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base). Besides that, the smi async clock should be prepared and enabled for
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SMI generation 1 to transform the smi clock into emi clock domain, but that is
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not needed for SMI generation 2.
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Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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"mediatek,mt6779-smi-common"
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"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
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"mediatek,mt8167-smi-common"
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"mediatek,mt8173-smi-common"
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"mediatek,mt8183-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
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for generation 2 smi HW as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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They may be the same if both source clocks are the same.
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- "async" : asynchronous clock, it help transform the smi clock into the emi
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clock domain, this clock is only needed by generation 1 smi HW.
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and these 2 option clocks for generation 2 smi HW:
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- "gals0": the path0 clock of GALS(Global Async Local Sync).
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- "gals1": the path1 clock of GALS(Global Async Local Sync).
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Here is the list which has this GALS: mt6779 and mt8183.
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Example:
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smi_common: smi@14022000 {
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compatible = "mediatek,mt8173-smi-common";
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reg = <0 0x14022000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_SMI_COMMON>,
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<&mmsys CLK_MM_SMI_COMMON>;
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clock-names = "apb", "smi";
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};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (c) 2020 MediaTek Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SMI (Smart Multimedia Interface) Common
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maintainers:
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- Yong Wu <yong.wu@mediatek.com>
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description: |
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The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
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MediaTek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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for generation 1, the register is at smi ao base(smi always on register
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base). Besides that, the smi async clock should be prepared and enabled for
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SMI generation 1 to transform the smi clock into emi clock domain, but that is
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not needed for SMI generation 2.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-smi-common
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- mediatek,mt2712-smi-common
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- mediatek,mt6779-smi-common
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- mediatek,mt8167-smi-common
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- mediatek,mt8173-smi-common
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- mediatek,mt8183-smi-common
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- description: for mt7623
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items:
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- const: mediatek,mt7623-smi-common
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- const: mediatek,mt2701-smi-common
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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description: |
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apb and smi are mandatory. the async is only for generation 1 smi HW.
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gals(global async local sync) also is optional, see below.
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minItems: 2
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maxItems: 4
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items:
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- description: apb is Advanced Peripheral Bus clock, It's the clock for
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setting the register.
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- description: smi is the clock for transfer data and command.
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- description: async is asynchronous clock, it help transform the smi
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clock into the emi clock domain.
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- description: gals0 is the path0 clock of gals.
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- description: gals1 is the path1 clock of gals.
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clock-names:
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minItems: 2
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maxItems: 4
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required:
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- compatible
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- reg
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- power-domains
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- clocks
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- clock-names
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allOf:
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- if: # only for gen1 HW
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2701-smi-common
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then:
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properties:
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clock:
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items:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: apb
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- const: smi
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- const: async
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- if: # for gen2 HW that have gals
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properties:
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compatible:
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enum:
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- mediatek,mt6779-smi-common
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- mediatek,mt8183-smi-common
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then:
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properties:
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clock:
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items:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: apb
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- const: smi
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- const: gals0
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- const: gals1
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else: # for gen2 HW that don't have gals
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properties:
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clock:
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items:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: apb
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- const: smi
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additionalProperties: false
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examples:
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- |+
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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smi_common: smi@14022000 {
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compatible = "mediatek,mt8173-smi-common";
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reg = <0x14022000 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_SMI_COMMON>,
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<&mmsys CLK_MM_SMI_COMMON>;
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clock-names = "apb", "smi";
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};
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@ -1,50 +0,0 @@
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SMI (Smart Multimedia Interface) Local Arbiter
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-larb"
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"mediatek,mt2712-smi-larb"
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"mediatek,mt6779-smi-larb"
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"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
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"mediatek,mt8167-smi-larb"
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"mediatek,mt8173-smi-larb"
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"mediatek,mt8183-smi-larb"
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- reg : the register and size of this local arbiter.
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- mediatek,smi : a phandle to the smi_common node.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names: must contain 2 entries, as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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and this optional clock name:
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- "gals": the clock for GALS(Global Async Local Sync).
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Here is the list which has this GALS: mt8183.
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Required property for mt2701, mt2712, mt6779, mt7623 and mt8167:
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- mediatek,larb-id :the hardware id of this larb.
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Example:
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larb1: larb@16010000 {
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compatible = "mediatek,mt8173-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&vdecsys CLK_VDEC_CKEN>,
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<&vdecsys CLK_VDEC_LARB_CKEN>;
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clock-names = "apb", "smi";
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};
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Example for mt2701:
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larb0: larb@14010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <0>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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@ -0,0 +1,130 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (c) 2020 MediaTek Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SMI (Smart Multimedia Interface) Local Arbiter
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maintainers:
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- Yong Wu <yong.wu@mediatek.com>
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description: |
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The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-smi-larb
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- mediatek,mt2712-smi-larb
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- mediatek,mt6779-smi-larb
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- mediatek,mt8167-smi-larb
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- mediatek,mt8173-smi-larb
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- mediatek,mt8183-smi-larb
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- description: for mt7623
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items:
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- const: mediatek,mt7623-smi-larb
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- const: mediatek,mt2701-smi-larb
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reg:
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maxItems: 1
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clocks:
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description: |
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apb and smi are mandatory. gals(global async local sync) is optional.
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minItems: 2
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maxItems: 3
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items:
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- description: apb is Advanced Peripheral Bus clock, It's the clock for
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setting the register.
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- description: smi is the clock for transfer data and command.
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- description: the clock for gals.
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clock-names:
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minItems: 2
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maxItems: 3
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power-domains:
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maxItems: 1
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mediatek,smi:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: a phandle to the smi_common node.
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mediatek,larb-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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description: the hardware id of this larb. It's only required when this
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hardward id is not consecutive from its M4U point of view.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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allOf:
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- if: # HW has gals
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properties:
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compatible:
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enum:
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- mediatek,mt8183-smi-larb
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then:
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properties:
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clock:
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items:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: apb
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- const: smi
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- const: gals
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else:
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properties:
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clock:
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items:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: apb
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- const: smi
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2701-smi-larb
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- mediatek,mt2712-smi-larb
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- mediatek,mt6779-smi-larb
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- mediatek,mt8167-smi-larb
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then:
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required:
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- mediatek,larb-id
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additionalProperties: false
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examples:
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- |+
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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larb1: larb@16010000 {
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compatible = "mediatek,mt8173-smi-larb";
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reg = <0x16010000 0x1000>;
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mediatek,smi = <&smi_common>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&vdecsys CLK_VDEC_CKEN>,
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<&vdecsys CLK_VDEC_LARB_CKEN>;
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clock-names = "apb", "smi";
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};
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