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arm64: fix "dc cvau" cache operation on errata-affected core

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The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Andre Przywara 2016-06-28 18:07:28 +01:00 • committed by Catalin Marinas
parent b82bfa4793
commit 290622efc7
2 changed files with 5 additions and 1 deletions
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4
arch/arm64/include/asm/alternative.h
View file

@ -133,6 +133,10 @@ void apply_alternatives(void *start, size_t length);
#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
.macro user_alt, label, oldinstr, newinstr, cond
9999: alternative_insn "\oldinstr", "\newinstr", \cond
_ASM_EXTABLE 9999b, \label
.endm
/* /*
* Generate the assembly for UAO alternatives with exception table entries. * Generate the assembly for UAO alternatives with exception table entries.

2
arch/arm64/mm/cache.S
View file

@ -52,7 +52,7 @@ ENTRY(__flush_cache_user_range)
sub x3, x2, #1 sub x3, x2, #1
bic x4, x0, x3 bic x4, x0, x3
1: 1:
USER(9f, dc cvau, x4 ) // clean D line to PoU user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
add x4, x4, x2 add x4, x4, x2
cmp x4, x1 cmp x4, x1
b.lo 1b b.lo 1b