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RISC-V Fixes for 6.14-rc5

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* A fix for cacheinfo DT probing to avoid reading non-boolean properties
   as booleans.
 * A fix for cpufeature to use bitmap_equal() instead of memcmp(), so
   unused bits are ignored.
 * Fixes for cmpxchg and futex cmpxchg that properly encode the sign
   extension requirements on inline asm, which results in spurious
   successes.  This manifests in at least inode_set_ctime_current, but is
   likely just a disaster waiting to happen.
 * A fix for the rseq selftests, which was using an invalid constraint.
 * A pair of fixes for signal frame size handling:
     * We were reserving space for an extra empty extension context
       header on systems with extended signal context, thus resulting in
       unnecessarily large allocations.
     * We weren't properly checking for available extensions before
       calculating the signal stack size, which resulted in undersized
       stack allocations on some systems (at least those with T-Head
       custom vectors).
 
 Also, we've added Alex as a reviewer.  He's been helping out a ton
 lately, thanks!
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Merge tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix for cacheinfo DT probing to avoid reading non-boolean
   properties as booleans.

 - A fix for cpufeature to use bitmap_equal() instead of memcmp(), so
   unused bits are ignored.

 - Fixes for cmpxchg and futex cmpxchg that properly encode the sign
   extension requirements on inline asm, which results in spurious
   successes. This manifests in at least inode_set_ctime_current, but is
   likely just a disaster waiting to happen.

 - A fix for the rseq selftests, which was using an invalid constraint.

 - A pair of fixes for signal frame size handling:

     - We were reserving space for an extra empty extension context
       header on systems with extended signal context, thus resulting in
       unnecessarily large allocations.

     - We weren't properly checking for available extensions before
       calculating the signal stack size, which resulted in undersized
       stack allocations on some systems (at least those with T-Head
       custom vectors).

Also, we've added Alex as a reviewer.  He's been helping out a ton
lately, thanks!

* tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  MAINTAINERS: Add myself as a riscv reviewer
  riscv: signal: fix signal_minsigstksz
  riscv: signal: fix signal frame size
  rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
  riscv/futex: sign extend compare value in atomic cmpxchg
  riscv/atomic: Do proper sign extension also for unsigned in arch_cmpxchg
  riscv: cpufeature: use bitmap_equal() instead of memcmp()
  riscv: cacheinfo: Use of_property_present() for non-boolean properties
This commit is contained in:
Linus Torvalds 2025-02-24 16:40:32 -08:00
commit 2a1944bff5
9 changed files with 15 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
MAINTAINERS
View file

@ -20328,6 +20328,7 @@ RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com> M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com> M: Palmer Dabbelt <palmer@dabbelt.com>
M: Albert Ou <aou@eecs.berkeley.edu> M: Albert Ou <aou@eecs.berkeley.edu>
R: Alexandre Ghiti <alex@ghiti.fr>
L: linux-riscv@lists.infradead.org L: linux-riscv@lists.infradead.org
S: Supported S: Supported
Q: https://patchwork.kernel.org/project/linux-riscv/list/ Q: https://patchwork.kernel.org/project/linux-riscv/list/

2
arch/riscv/include/asm/cmpxchg.h
View file

@ -231,7 +231,7 @@
__arch_cmpxchg(".w", ".w" sc_sfx, ".w" cas_sfx, \ __arch_cmpxchg(".w", ".w" sc_sfx, ".w" cas_sfx, \
sc_prepend, sc_append, \ sc_prepend, sc_append, \
cas_prepend, cas_append, \ cas_prepend, cas_append, \
__ret, __ptr, (long), __old, __new); \ __ret, __ptr, (long)(int)(long), __old, __new); \
break; \ break; \
case 8: \ case 8: \
__arch_cmpxchg(".d", ".d" sc_sfx, ".d" cas_sfx, \ __arch_cmpxchg(".d", ".d" sc_sfx, ".d" cas_sfx, \

2
arch/riscv/include/asm/futex.h
View file

@ -93,7 +93,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %[r]) \ _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %[r]) \
_ASM_EXTABLE_UACCESS_ERR(2b, 3b, %[r]) \ _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %[r]) \
: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp) : [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
: [ov] "Jr" (oldval), [nv] "Jr" (newval) : [ov] "Jr" ((long)(int)oldval), [nv] "Jr" (newval)
: "memory"); : "memory");
__disable_user_access(); __disable_user_access();

12
arch/riscv/kernel/cacheinfo.c
View file

@ -108,11 +108,11 @@ int populate_cache_leaves(unsigned int cpu)
if (!np) if (!np)
return -ENOENT; return -ENOENT;
if (of_property_read_bool(np, "cache-size")) if (of_property_present(np, "cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size")) if (of_property_present(np, "i-cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
if (of_property_read_bool(np, "d-cache-size")) if (of_property_present(np, "d-cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
prev = np; prev = np;
@ -125,11 +125,11 @@ int populate_cache_leaves(unsigned int cpu)
break; break;
if (level <= levels) if (level <= levels)
break; break;
if (of_property_read_bool(np, "cache-size")) if (of_property_present(np, "cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size")) if (of_property_present(np, "i-cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
if (of_property_read_bool(np, "d-cache-size")) if (of_property_present(np, "d-cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
levels = level; levels = level;
} }

2
arch/riscv/kernel/cpufeature.c
View file

@ -479,7 +479,7 @@ static void __init riscv_resolve_isa(unsigned long *source_isa,
if (bit < RISCV_ISA_EXT_BASE) if (bit < RISCV_ISA_EXT_BASE)
*this_hwcap |= isa2hwcap[bit]; *this_hwcap |= isa2hwcap[bit];
} }
} while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa))); } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
} }
static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap) static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)

2
arch/riscv/kernel/setup.c
View file

@ -322,8 +322,8 @@ void __init setup_arch(char **cmdline_p)
riscv_init_cbo_blocksizes(); riscv_init_cbo_blocksizes();
riscv_fill_hwcap(); riscv_fill_hwcap();
init_rt_signal_env();
apply_boot_alternatives(); apply_boot_alternatives();
init_rt_signal_env();
if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
riscv_isa_extension_available(NULL, ZICBOM)) riscv_isa_extension_available(NULL, ZICBOM))

6
arch/riscv/kernel/signal.c
View file

@ -215,12 +215,6 @@ static size_t get_rt_frame_size(bool cal_all)
if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) if (cal_all || riscv_v_vstate_query(task_pt_regs(current)))
total_context_size += riscv_v_sc_size; total_context_size += riscv_v_sc_size;
} }
/*
* Preserved a __riscv_ctx_hdr for END signal context header if an
* extension uses __riscv_extra_ext_header
*/
if (total_context_size)
total_context_size += sizeof(struct __riscv_ctx_hdr);
frame_size += total_context_size; frame_size += total_context_size;

6
tools/testing/selftests/rseq/rseq-riscv-bits.h
View file

@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
#ifdef RSEQ_COMPARE_TWICE #ifdef RSEQ_COMPARE_TWICE
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
#endif #endif
RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3) RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
RSEQ_INJECT_ASM(4) RSEQ_INJECT_ASM(4)
RSEQ_ASM_DEFINE_ABORT(4, abort) RSEQ_ASM_DEFINE_ABORT(4, abort)
: /* gcc asm goto does not allow outputs */ : /* gcc asm goto does not allow outputs */
@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD), [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr), [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
[ptr] "r" (ptr), [ptr] "r" (ptr),
[off] "er" (off), [off] "r" (off),
[inc] "er" (inc) [inc] "r" (inc)
RSEQ_INJECT_INPUT RSEQ_INJECT_INPUT
: "memory", RSEQ_ASM_TMP_REG_1 : "memory", RSEQ_ASM_TMP_REG_1
RSEQ_INJECT_CLOBBER RSEQ_INJECT_CLOBBER

2
tools/testing/selftests/rseq/rseq-riscv.h
View file

@ -158,7 +158,7 @@ do { \
"bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \
"333:\n" "333:\n"
#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \ #define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
"mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \
RSEQ_ASM_OP_R_ADD(off) \ RSEQ_ASM_OP_R_ADD(off) \
REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \ REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \