can: ctucanfd: add support for CTU CAN FD open-source IP core - bus independent part.
This driver adds support for the CTU CAN FD open-source IP core. More documentation and core sources at project page (https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core). The core integration to Xilinx Zynq system as platform driver is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top). Implementation on Intel FPGA based PCI Express board is available from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd). More about CAN bus related projects used and developed at CTU FEE at https://canbus.pages.fel.cvut.cz/ . Link: https://lore.kernel.org/all/1906e4941560ae2ce4b8d181131fd4963aa31611.1647904780.git.pisa@cmp.felk.cvut.cz Signed-off-by: Martin Jerabek <martin.jerabek01@gmail.com> Signed-off-by: Ondrej Ille <ondrej.ille@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Martin Jerabek
Marc Kleine-Budde
parent
1da9d6e35b
commit
2dcb8e8782
8 changed files with 1995 additions and 0 deletions
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@ -170,6 +170,7 @@ config PCH_CAN
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source "drivers/net/can/c_can/Kconfig"
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source "drivers/net/can/cc770/Kconfig"
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source "drivers/net/can/ctucanfd/Kconfig"
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source "drivers/net/can/ifi_canfd/Kconfig"
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source "drivers/net/can/m_can/Kconfig"
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source "drivers/net/can/mscan/Kconfig"
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@ -16,6 +16,7 @@ obj-y += softing/
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obj-$(CONFIG_CAN_AT91) += at91_can.o
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obj-$(CONFIG_CAN_CC770) += cc770/
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obj-$(CONFIG_CAN_C_CAN) += c_can/
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obj-$(CONFIG_CAN_CTUCANFD) += ctucanfd/
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obj-$(CONFIG_CAN_FLEXCAN) += flexcan/
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obj-$(CONFIG_CAN_GRCAN) += grcan.o
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obj-$(CONFIG_CAN_IFI_CANFD) += ifi_canfd/
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12
drivers/net/can/ctucanfd/Kconfig
Normal file
12
drivers/net/can/ctucanfd/Kconfig
Normal file
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@ -0,0 +1,12 @@
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config CAN_CTUCANFD
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tristate "CTU CAN-FD IP core"
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help
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This driver adds support for the CTU CAN FD open-source IP core.
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More documentation and core sources at project page
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(https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core).
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The core integration to Xilinx Zynq system as platform driver
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is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
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Implementation on Intel FPGA-based PCI Express board is available
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from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
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on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
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Guidepost CTU FEE CAN bus projects page https://canbus.pages.fel.cvut.cz/ .
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7
drivers/net/can/ctucanfd/Makefile
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7
drivers/net/can/ctucanfd/Makefile
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Makefile for the CTU CAN-FD IP module drivers
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#
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obj-$(CONFIG_CAN_CTUCANFD) := ctucanfd.o
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ctucanfd-y := ctucanfd_base.o
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82
drivers/net/can/ctucanfd/ctucanfd.h
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82
drivers/net/can/ctucanfd/ctucanfd.h
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@ -0,0 +1,82 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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#ifndef __CTUCANFD__
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#define __CTUCANFD__
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#include <linux/netdevice.h>
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#include <linux/can/dev.h>
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#include <linux/list.h>
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enum ctu_can_fd_can_registers;
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struct ctucan_priv {
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struct can_priv can; /* must be first member! */
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void __iomem *mem_base;
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u32 (*read_reg)(struct ctucan_priv *priv,
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enum ctu_can_fd_can_registers reg);
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void (*write_reg)(struct ctucan_priv *priv,
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enum ctu_can_fd_can_registers reg, u32 val);
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unsigned int txb_head;
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unsigned int txb_tail;
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u32 txb_prio;
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unsigned int ntxbufs;
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spinlock_t tx_lock; /* spinlock to serialize allocation and processing of TX buffers */
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struct napi_struct napi;
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struct device *dev;
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struct clk *can_clk;
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int irq_flags;
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unsigned long drv_flags;
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u32 rxfrm_first_word;
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struct list_head peers_on_pdev;
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};
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/**
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* ctucan_probe_common - Device type independent registration call
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*
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* This function does all the memory allocation and registration for the CAN
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* device.
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*
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* @dev: Handle to the generic device structure
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* @addr: Base address of CTU CAN FD core address
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* @irq: Interrupt number
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* @ntxbufs: Number of implemented Tx buffers
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* @can_clk_rate: Clock rate, if 0 then clock are taken from device node
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* @pm_enable_call: Whether pm_runtime_enable should be called
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* @set_drvdata_fnc: Function to set network driver data for physical device
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*
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* Return: 0 on success and failure value on error
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*/
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int ctucan_probe_common(struct device *dev, void __iomem *addr,
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int irq, unsigned int ntxbufs,
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unsigned long can_clk_rate,
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int pm_enable_call,
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void (*set_drvdata_fnc)(struct device *dev,
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struct net_device *ndev));
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int ctucan_suspend(struct device *dev) __maybe_unused;
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int ctucan_resume(struct device *dev) __maybe_unused;
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#endif /*__CTUCANFD__*/
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1490
drivers/net/can/ctucanfd/ctucanfd_base.c
Normal file
1490
drivers/net/can/ctucanfd/ctucanfd_base.c
Normal file
File diff suppressed because it is too large
Load diff
77
drivers/net/can/ctucanfd/ctucanfd_kframe.h
Normal file
77
drivers/net/can/ctucanfd/ctucanfd_kframe.h
Normal file
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@ -0,0 +1,77 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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/* This file is autogenerated, DO NOT EDIT! */
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#ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
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#define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
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#include <linux/bits.h>
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/* CAN_Frame_format memory map */
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enum ctu_can_fd_can_frame_format {
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CTUCANFD_FRAME_FORMAT_W = 0x0,
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CTUCANFD_IDENTIFIER_W = 0x4,
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CTUCANFD_TIMESTAMP_L_W = 0x8,
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CTUCANFD_TIMESTAMP_U_W = 0xc,
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CTUCANFD_DATA_1_4_W = 0x10,
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CTUCANFD_DATA_5_8_W = 0x14,
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CTUCANFD_DATA_61_64_W = 0x4c,
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};
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/* CAN_FD_Frame_format memory region */
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/* FRAME_FORMAT_W registers */
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#define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0)
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#define REG_FRAME_FORMAT_W_RTR BIT(5)
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#define REG_FRAME_FORMAT_W_IDE BIT(6)
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#define REG_FRAME_FORMAT_W_FDF BIT(7)
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#define REG_FRAME_FORMAT_W_BRS BIT(9)
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#define REG_FRAME_FORMAT_W_ESI_RSV BIT(10)
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#define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11)
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/* IDENTIFIER_W registers */
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#define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0)
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#define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18)
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/* TIMESTAMP_L_W registers */
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#define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0)
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/* TIMESTAMP_U_W registers */
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#define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0)
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/* DATA_1_4_W registers */
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#define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0)
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#define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8)
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#define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16)
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#define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24)
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/* DATA_5_8_W registers */
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#define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0)
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#define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8)
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#define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16)
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#define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24)
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/* DATA_61_64_W registers */
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#define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0)
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#define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8)
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#define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16)
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#define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24)
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#endif
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325
drivers/net/can/ctucanfd/ctucanfd_kregs.h
Normal file
325
drivers/net/can/ctucanfd/ctucanfd_kregs.h
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@ -0,0 +1,325 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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/* This file is autogenerated, DO NOT EDIT! */
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#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
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#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
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#include <linux/bits.h>
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/* CAN_Registers memory map */
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enum ctu_can_fd_can_registers {
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CTUCANFD_DEVICE_ID = 0x0,
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CTUCANFD_VERSION = 0x2,
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CTUCANFD_MODE = 0x4,
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CTUCANFD_SETTINGS = 0x6,
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CTUCANFD_STATUS = 0x8,
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CTUCANFD_COMMAND = 0xc,
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CTUCANFD_INT_STAT = 0x10,
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CTUCANFD_INT_ENA_SET = 0x14,
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CTUCANFD_INT_ENA_CLR = 0x18,
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CTUCANFD_INT_MASK_SET = 0x1c,
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CTUCANFD_INT_MASK_CLR = 0x20,
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CTUCANFD_BTR = 0x24,
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CTUCANFD_BTR_FD = 0x28,
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CTUCANFD_EWL = 0x2c,
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CTUCANFD_ERP = 0x2d,
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CTUCANFD_FAULT_STATE = 0x2e,
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CTUCANFD_REC = 0x30,
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CTUCANFD_TEC = 0x32,
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CTUCANFD_ERR_NORM = 0x34,
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CTUCANFD_ERR_FD = 0x36,
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CTUCANFD_CTR_PRES = 0x38,
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CTUCANFD_FILTER_A_MASK = 0x3c,
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CTUCANFD_FILTER_A_VAL = 0x40,
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CTUCANFD_FILTER_B_MASK = 0x44,
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CTUCANFD_FILTER_B_VAL = 0x48,
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CTUCANFD_FILTER_C_MASK = 0x4c,
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CTUCANFD_FILTER_C_VAL = 0x50,
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CTUCANFD_FILTER_RAN_LOW = 0x54,
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CTUCANFD_FILTER_RAN_HIGH = 0x58,
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CTUCANFD_FILTER_CONTROL = 0x5c,
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CTUCANFD_FILTER_STATUS = 0x5e,
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CTUCANFD_RX_MEM_INFO = 0x60,
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CTUCANFD_RX_POINTERS = 0x64,
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CTUCANFD_RX_STATUS = 0x68,
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CTUCANFD_RX_SETTINGS = 0x6a,
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CTUCANFD_RX_DATA = 0x6c,
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CTUCANFD_TX_STATUS = 0x70,
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CTUCANFD_TX_COMMAND = 0x74,
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CTUCANFD_TX_PRIORITY = 0x78,
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CTUCANFD_ERR_CAPT = 0x7c,
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CTUCANFD_ALC = 0x7e,
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CTUCANFD_TRV_DELAY = 0x80,
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CTUCANFD_SSP_CFG = 0x82,
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CTUCANFD_RX_FR_CTR = 0x84,
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CTUCANFD_TX_FR_CTR = 0x88,
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CTUCANFD_DEBUG_REGISTER = 0x8c,
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CTUCANFD_YOLO_REG = 0x90,
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CTUCANFD_TIMESTAMP_LOW = 0x94,
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CTUCANFD_TIMESTAMP_HIGH = 0x98,
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CTUCANFD_TXTB1_DATA_1 = 0x100,
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CTUCANFD_TXTB1_DATA_2 = 0x104,
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CTUCANFD_TXTB1_DATA_20 = 0x14c,
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CTUCANFD_TXTB2_DATA_1 = 0x200,
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CTUCANFD_TXTB2_DATA_2 = 0x204,
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CTUCANFD_TXTB2_DATA_20 = 0x24c,
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CTUCANFD_TXTB3_DATA_1 = 0x300,
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CTUCANFD_TXTB3_DATA_2 = 0x304,
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CTUCANFD_TXTB3_DATA_20 = 0x34c,
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CTUCANFD_TXTB4_DATA_1 = 0x400,
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CTUCANFD_TXTB4_DATA_2 = 0x404,
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CTUCANFD_TXTB4_DATA_20 = 0x44c,
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};
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/* Control_registers memory region */
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/* DEVICE_ID VERSION registers */
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#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
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#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
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#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
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/* MODE SETTINGS registers */
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#define REG_MODE_RST BIT(0)
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#define REG_MODE_BMM BIT(1)
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#define REG_MODE_STM BIT(2)
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#define REG_MODE_AFM BIT(3)
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#define REG_MODE_FDE BIT(4)
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#define REG_MODE_ACF BIT(7)
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#define REG_MODE_TSTM BIT(8)
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#define REG_MODE_RTRLE BIT(16)
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#define REG_MODE_RTRTH GENMASK(20, 17)
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#define REG_MODE_ILBP BIT(21)
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#define REG_MODE_ENA BIT(22)
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#define REG_MODE_NISOFD BIT(23)
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#define REG_MODE_PEX BIT(24)
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#define REG_MODE_TBFBO BIT(25)
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#define REG_MODE_FDRF BIT(26)
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/* STATUS registers */
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#define REG_STATUS_RXNE BIT(0)
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#define REG_STATUS_DOR BIT(1)
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#define REG_STATUS_TXNF BIT(2)
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#define REG_STATUS_EFT BIT(3)
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#define REG_STATUS_RXS BIT(4)
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#define REG_STATUS_TXS BIT(5)
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#define REG_STATUS_EWL BIT(6)
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#define REG_STATUS_IDLE BIT(7)
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#define REG_STATUS_PEXS BIT(8)
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/* COMMAND registers */
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#define REG_COMMAND_RRB BIT(2)
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#define REG_COMMAND_CDO BIT(3)
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#define REG_COMMAND_ERCRST BIT(4)
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#define REG_COMMAND_RXFCRST BIT(5)
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#define REG_COMMAND_TXFCRST BIT(6)
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#define REG_COMMAND_CPEXS BIT(7)
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/* INT_STAT registers */
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#define REG_INT_STAT_RXI BIT(0)
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#define REG_INT_STAT_TXI BIT(1)
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#define REG_INT_STAT_EWLI BIT(2)
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#define REG_INT_STAT_DOI BIT(3)
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#define REG_INT_STAT_FCSI BIT(4)
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#define REG_INT_STAT_ALI BIT(5)
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#define REG_INT_STAT_BEI BIT(6)
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#define REG_INT_STAT_OFI BIT(7)
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#define REG_INT_STAT_RXFI BIT(8)
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#define REG_INT_STAT_BSI BIT(9)
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#define REG_INT_STAT_RBNEI BIT(10)
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#define REG_INT_STAT_TXBHCI BIT(11)
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/* INT_ENA_SET registers */
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#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
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/* INT_ENA_CLR registers */
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#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
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/* INT_MASK_SET registers */
|
||||
#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
|
||||
|
||||
/* INT_MASK_CLR registers */
|
||||
#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
|
||||
|
||||
/* BTR registers */
|
||||
#define REG_BTR_PROP GENMASK(6, 0)
|
||||
#define REG_BTR_PH1 GENMASK(12, 7)
|
||||
#define REG_BTR_PH2 GENMASK(18, 13)
|
||||
#define REG_BTR_BRP GENMASK(26, 19)
|
||||
#define REG_BTR_SJW GENMASK(31, 27)
|
||||
|
||||
/* BTR_FD registers */
|
||||
#define REG_BTR_FD_PROP_FD GENMASK(5, 0)
|
||||
#define REG_BTR_FD_PH1_FD GENMASK(11, 7)
|
||||
#define REG_BTR_FD_PH2_FD GENMASK(17, 13)
|
||||
#define REG_BTR_FD_BRP_FD GENMASK(26, 19)
|
||||
#define REG_BTR_FD_SJW_FD GENMASK(31, 27)
|
||||
|
||||
/* EWL ERP FAULT_STATE registers */
|
||||
#define REG_EWL_EW_LIMIT GENMASK(7, 0)
|
||||
#define REG_EWL_ERP_LIMIT GENMASK(15, 8)
|
||||
#define REG_EWL_ERA BIT(16)
|
||||
#define REG_EWL_ERP BIT(17)
|
||||
#define REG_EWL_BOF BIT(18)
|
||||
|
||||
/* REC TEC registers */
|
||||
#define REG_REC_REC_VAL GENMASK(8, 0)
|
||||
#define REG_REC_TEC_VAL GENMASK(24, 16)
|
||||
|
||||
/* ERR_NORM ERR_FD registers */
|
||||
#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
|
||||
#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
|
||||
|
||||
/* CTR_PRES registers */
|
||||
#define REG_CTR_PRES_CTPV GENMASK(8, 0)
|
||||
#define REG_CTR_PRES_PTX BIT(9)
|
||||
#define REG_CTR_PRES_PRX BIT(10)
|
||||
#define REG_CTR_PRES_ENORM BIT(11)
|
||||
#define REG_CTR_PRES_EFD BIT(12)
|
||||
|
||||
/* FILTER_A_MASK registers */
|
||||
#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_A_VAL registers */
|
||||
#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_B_MASK registers */
|
||||
#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_B_VAL registers */
|
||||
#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_C_MASK registers */
|
||||
#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_C_VAL registers */
|
||||
#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_RAN_LOW registers */
|
||||
#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_RAN_HIGH registers */
|
||||
#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
|
||||
|
||||
/* FILTER_CONTROL FILTER_STATUS registers */
|
||||
#define REG_FILTER_CONTROL_FANB BIT(0)
|
||||
#define REG_FILTER_CONTROL_FANE BIT(1)
|
||||
#define REG_FILTER_CONTROL_FAFB BIT(2)
|
||||
#define REG_FILTER_CONTROL_FAFE BIT(3)
|
||||
#define REG_FILTER_CONTROL_FBNB BIT(4)
|
||||
#define REG_FILTER_CONTROL_FBNE BIT(5)
|
||||
#define REG_FILTER_CONTROL_FBFB BIT(6)
|
||||
#define REG_FILTER_CONTROL_FBFE BIT(7)
|
||||
#define REG_FILTER_CONTROL_FCNB BIT(8)
|
||||
#define REG_FILTER_CONTROL_FCNE BIT(9)
|
||||
#define REG_FILTER_CONTROL_FCFB BIT(10)
|
||||
#define REG_FILTER_CONTROL_FCFE BIT(11)
|
||||
#define REG_FILTER_CONTROL_FRNB BIT(12)
|
||||
#define REG_FILTER_CONTROL_FRNE BIT(13)
|
||||
#define REG_FILTER_CONTROL_FRFB BIT(14)
|
||||
#define REG_FILTER_CONTROL_FRFE BIT(15)
|
||||
#define REG_FILTER_CONTROL_SFA BIT(16)
|
||||
#define REG_FILTER_CONTROL_SFB BIT(17)
|
||||
#define REG_FILTER_CONTROL_SFC BIT(18)
|
||||
#define REG_FILTER_CONTROL_SFR BIT(19)
|
||||
|
||||
/* RX_MEM_INFO registers */
|
||||
#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
|
||||
#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
|
||||
|
||||
/* RX_POINTERS registers */
|
||||
#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
|
||||
#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
|
||||
|
||||
/* RX_STATUS RX_SETTINGS registers */
|
||||
#define REG_RX_STATUS_RXE BIT(0)
|
||||
#define REG_RX_STATUS_RXF BIT(1)
|
||||
#define REG_RX_STATUS_RXMOF BIT(2)
|
||||
#define REG_RX_STATUS_RXFRC GENMASK(14, 4)
|
||||
#define REG_RX_STATUS_RTSOP BIT(16)
|
||||
|
||||
/* RX_DATA registers */
|
||||
#define REG_RX_DATA_RX_DATA GENMASK(31, 0)
|
||||
|
||||
/* TX_STATUS registers */
|
||||
#define REG_TX_STATUS_TX1S GENMASK(3, 0)
|
||||
#define REG_TX_STATUS_TX2S GENMASK(7, 4)
|
||||
#define REG_TX_STATUS_TX3S GENMASK(11, 8)
|
||||
#define REG_TX_STATUS_TX4S GENMASK(15, 12)
|
||||
|
||||
/* TX_COMMAND registers */
|
||||
#define REG_TX_COMMAND_TXCE BIT(0)
|
||||
#define REG_TX_COMMAND_TXCR BIT(1)
|
||||
#define REG_TX_COMMAND_TXCA BIT(2)
|
||||
#define REG_TX_COMMAND_TXB1 BIT(8)
|
||||
#define REG_TX_COMMAND_TXB2 BIT(9)
|
||||
#define REG_TX_COMMAND_TXB3 BIT(10)
|
||||
#define REG_TX_COMMAND_TXB4 BIT(11)
|
||||
|
||||
/* TX_PRIORITY registers */
|
||||
#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
|
||||
#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
|
||||
#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
|
||||
#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
|
||||
|
||||
/* ERR_CAPT ALC registers */
|
||||
#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
|
||||
#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
|
||||
#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
|
||||
#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
|
||||
|
||||
/* TRV_DELAY SSP_CFG registers */
|
||||
#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
|
||||
#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
|
||||
#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
|
||||
|
||||
/* RX_FR_CTR registers */
|
||||
#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
|
||||
|
||||
/* TX_FR_CTR registers */
|
||||
#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
|
||||
|
||||
/* DEBUG_REGISTER registers */
|
||||
#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
|
||||
#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
|
||||
#define REG_DEBUG_REGISTER_PC_ARB BIT(6)
|
||||
#define REG_DEBUG_REGISTER_PC_CON BIT(7)
|
||||
#define REG_DEBUG_REGISTER_PC_DAT BIT(8)
|
||||
#define REG_DEBUG_REGISTER_PC_STC BIT(9)
|
||||
#define REG_DEBUG_REGISTER_PC_CRC BIT(10)
|
||||
#define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
|
||||
#define REG_DEBUG_REGISTER_PC_ACK BIT(12)
|
||||
#define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
|
||||
#define REG_DEBUG_REGISTER_PC_EOF BIT(14)
|
||||
#define REG_DEBUG_REGISTER_PC_INT BIT(15)
|
||||
#define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
|
||||
#define REG_DEBUG_REGISTER_PC_OVR BIT(17)
|
||||
#define REG_DEBUG_REGISTER_PC_SOF BIT(18)
|
||||
|
||||
/* YOLO_REG registers */
|
||||
#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
|
||||
|
||||
/* TIMESTAMP_LOW registers */
|
||||
#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
|
||||
|
||||
/* TIMESTAMP_HIGH registers */
|
||||
#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue