From e79c58975c27d58d7683937538bcc6b547e1829d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Wed, 20 Oct 2021 12:46:54 +0300 Subject: [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node Add RTC node. Signed-off-by: Eugen Hristev [claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers compared with sam9x60] Signed-off-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211020094656.3343242-2-claudiu.beznea@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index c9725d080e20..0912219ed5a1 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -130,6 +130,13 @@ reg = <0xe001d060 0x48>; }; + rtc: rtc@e001d0a8 { + compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d0a8 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + ps_wdt: watchdog@e001d180 { compatible = "microchip,sama7g5-wdt"; reg = <0xe001d180 0x24>; From 9430ff34385e285984711fccb2226771cbc675fb Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 20 Oct 2021 12:46:55 +0300 Subject: [PATCH 2/3] ARM: dts: at91: sama7g5: add tcb nodes Add TCB nodes. Signed-off-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211020094656.3343242-3-claudiu.beznea@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 0912219ed5a1..c75c7d7c2842 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -144,6 +144,16 @@ clocks = <&clk32k 0>; }; + tcb1: timer@e0800000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0800000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; @@ -461,6 +471,16 @@ status = "disabled"; }; + tcb0: timer@e2814000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2814000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + flx8: flexcom@e2818000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2818000 0x200>; From f3c0366411d6893360be21a7544595bf275bc9b2 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 20 Oct 2021 12:46:56 +0300 Subject: [PATCH 3/3] ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality. PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be used as a fallback only in case PIT64B will fail to probe. Signed-off-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211020094656.3343242-4-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index c46be165f2ba..902036a50e2e 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -654,6 +654,18 @@ status = "okay"; }; +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + &trng { status = "okay"; };