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drm/amd/display: Fix DCN3 B0 DP Alt Mapping

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[Why]
DCN3 B0 has a mux, which redirects PHYC and PHYD to PHYF and PHYG.

[How]
Fix DIG mapping.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
(cherry picked from commit 4b7786d87f)
This commit is contained in:
Liu, Zhan 2021-09-02 15:08:29 -04:00 • committed by Alex Deucher
parent 45d65c0f09
commit 2fe9a0e117
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View file

@ -1284,6 +1284,12 @@ static struct stream_encoder *dcn31_stream_encoder_create(
if (!enc1 || !vpg || !afmt) if (!enc1 || !vpg || !afmt)
return NULL; return NULL;
if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
eng_id = eng_id + 3; // For B0 only. C->F, D->G.
}
dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
eng_id, vpg, afmt, eng_id, vpg, afmt,
&stream_enc_regs[eng_id], &stream_enc_regs[eng_id],