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ARM: dts: da850,da850-evm: Add an aemif node and use it for the NAND

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Currently the davinci da8xx boards use the mach-davinci aemif code.
Instantiating an aemif node into the DT allows to use the ti-aemif
memory driver and is another step to better DT support.
This change adds an aemif node in the dtsi while retiring the nand_cs3
node. The NAND is now instantiated in the dts as a subnode of the aemif
one along with its pins.

Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Karl Beldan 2016-08-16 22:33:37 +00:00 • committed by Sekhar Nori
parent 44524a010a
commit 31e3a8817b
2 changed files with 52 additions and 32 deletions
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49
arch/arm/boot/dts/da850-evm.dts
View file

@ -29,6 +29,20 @@
0x04 0x00011000 0x000ff000 0x04 0x00011000 0x000ff000
>; >;
}; };
nand_pins: nand_pins {
pinctrl-single,bits = <
/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
0x1c 0x10110110 0xf0ff0ff0
/*
* EMA_D[0], EMA_D[1], EMA_D[2],
* EMA_D[3], EMA_D[4], EMA_D[5],
* EMA_D[6], EMA_D[7]
*/
0x24 0x11111111 0xffffffff
/* EMA_A[1], EMA_A[2] */
0x30 0x01100000 0x0ff00000
>;
};
}; };
serial0: serial@42000 { serial0: serial@42000 {
status = "okay"; status = "okay";
@ -131,11 +145,6 @@
status = "okay"; status = "okay";
}; };
}; };
nand_cs3@62000000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_cs3_pins>;
};
vbat: fixedregulator@0 { vbat: fixedregulator@0 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vbat"; regulator-name = "vbat";
@ -250,3 +259,33 @@
&edma1 { &edma1 {
ti,edma-reserved-slot-ranges = <32 90>; ti,edma-reserved-slot-ranges = <32 90>;
}; };
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
status = "ok";
cs3 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <3>;
nand@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x02000000 0x02000000
1 0x00000000 0x00008000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
};
};
};

35
arch/arm/boot/dts/da850.dtsi
View file

@ -77,22 +77,6 @@
0x10 0x00220000 0x00ff0000 0x10 0x00220000 0x00ff0000
>; >;
}; };
nand_cs3_pins: pinmux_nand_pins {
pinctrl-single,bits = <
/* EMA_OE, EMA_WE */
0x1c 0x00110000 0x00ff0000
/* EMA_CS[4],EMA_CS[3]*/
0x1c 0x00000110 0x00000ff0
/*
* EMA_D[0], EMA_D[1], EMA_D[2],
* EMA_D[3], EMA_D[4], EMA_D[5],
* EMA_D[6], EMA_D[7]
*/
0x24 0x11111111 0xffffffff
/* EMA_A[1], EMA_A[2] */
0x30 0x01100000 0x0ff00000
>;
};
i2c0_pins: pinmux_i2c0_pins { i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,bits = < pinctrl-single,bits = <
/* I2C0_SDA,I2C0_SCL */ /* I2C0_SDA,I2C0_SCL */
@ -416,17 +400,14 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
}; };
nand_cs3@62000000 { aemif: aemif@68000000 {
compatible = "ti,davinci-nand"; compatible = "ti,da850-aemif";
reg = <0x62000000 0x807ff #address-cells = <2>;
0x68000000 0x8000>; #size-cells = <1>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>; reg = <0x68000000 0x00008000>;
ti,davinci-mask-cle = <0>; ranges = <0 0 0x60000000 0x08000000
ti,davinci-mask-chipsel = <0>; 1 0 0x68000000 0x00008000>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
status = "disabled"; status = "disabled";
}; };
}; };