net: stmmac: fix FPE events losing
The status bits of register MAC_FPE_CTRL_STS are clear on read. Using
32-bit read for MAC_FPE_CTRL_STS in dwmac5_fpe_configure() and
dwmac5_fpe_send_mpacket() clear the status bits. Then the stmmac interrupt
handler missing FPE event status and leads to FPE handshaking failure and
retries.
To avoid clear status bits of MAC_FPE_CTRL_STS in dwmac5_fpe_configure()
and dwmac5_fpe_send_mpacket(), add fpe_csr to stmmac_fpe_cfg structure to
cache the control bits of MAC_FPE_CTRL_STS and to avoid reading
MAC_FPE_CTRL_STS in those methods.
Fixes: 5a5586112b
("net: stmmac: support FPE link partner hand-shaking procedure")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Jianheng Zhang <Jianheng.Zhang@synopsys.com>
Link: https://lore.kernel.org/r/CY5PR12MB637225A7CF529D5BE0FBE59CBF81A@CY5PR12MB6372.namprd12.prod.outlook.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
adbf100fc4
commit
37e4b8df27
7 changed files with 36 additions and 30 deletions
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@ -710,28 +710,22 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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}
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}
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}
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}
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
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u32 num_txq, u32 num_rxq,
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bool enable)
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bool enable)
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{
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{
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u32 value;
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u32 value;
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if (!enable) {
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if (enable) {
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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cfg->fpe_csr = EFPE;
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value &= ~EFPE;
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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return;
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}
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value = readl(ioaddr + GMAC_RXQ_CTRL1);
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value = readl(ioaddr + GMAC_RXQ_CTRL1);
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value &= ~GMAC_RXQCTRL_FPRQ;
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value &= ~GMAC_RXQCTRL_FPRQ;
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value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
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value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
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writel(value, ioaddr + GMAC_RXQ_CTRL1);
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writel(value, ioaddr + GMAC_RXQ_CTRL1);
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} else {
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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cfg->fpe_csr = 0;
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value |= EFPE;
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}
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS);
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}
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}
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int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
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int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
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@ -741,6 +735,9 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
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status = FPE_EVENT_UNKNOWN;
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status = FPE_EVENT_UNKNOWN;
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/* Reads from the MAC_FPE_CTRL_STS register should only be performed
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* here, since the status flags of MAC_FPE_CTRL_STS are "clear on read"
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*/
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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if (value & TRSP) {
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if (value & TRSP) {
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@ -766,19 +763,15 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
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return status;
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return status;
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}
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}
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void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, enum stmmac_mpacket_type type)
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void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
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enum stmmac_mpacket_type type)
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{
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{
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u32 value;
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u32 value = cfg->fpe_csr;
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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if (type == MPACKET_VERIFY)
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if (type == MPACKET_VERIFY) {
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value &= ~SRSP;
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value |= SVER;
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value |= SVER;
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} else {
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else if (type == MPACKET_RESPONSE)
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value &= ~SVER;
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value |= SRSP;
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value |= SRSP;
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}
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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}
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}
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@ -153,9 +153,11 @@ int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate);
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unsigned int ptp_rate);
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void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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struct stmmac_extra_stats *x, u32 txqcnt);
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struct stmmac_extra_stats *x, u32 txqcnt);
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
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u32 num_txq, u32 num_rxq,
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bool enable);
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bool enable);
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void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
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void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
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struct stmmac_fpe_cfg *cfg,
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enum stmmac_mpacket_type type);
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enum stmmac_mpacket_type type);
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int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
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int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
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@ -1484,7 +1484,8 @@ static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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return 0;
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return 0;
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}
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}
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static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 num_txq,
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static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
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u32 num_txq,
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u32 num_rxq, bool enable)
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u32 num_rxq, bool enable)
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{
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{
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u32 value;
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u32 value;
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@ -412,9 +412,11 @@ struct stmmac_ops {
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unsigned int ptp_rate);
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unsigned int ptp_rate);
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void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev,
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void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev,
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struct stmmac_extra_stats *x, u32 txqcnt);
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struct stmmac_extra_stats *x, u32 txqcnt);
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void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
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u32 num_txq, u32 num_rxq,
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bool enable);
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bool enable);
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void (*fpe_send_mpacket)(void __iomem *ioaddr,
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void (*fpe_send_mpacket)(void __iomem *ioaddr,
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struct stmmac_fpe_cfg *cfg,
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enum stmmac_mpacket_type type);
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enum stmmac_mpacket_type type);
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int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev);
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int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev);
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};
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};
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@ -964,7 +964,8 @@ static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
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bool *hs_enable = &fpe_cfg->hs_enable;
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bool *hs_enable = &fpe_cfg->hs_enable;
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if (is_up && *hs_enable) {
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if (is_up && *hs_enable) {
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stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
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stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg,
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MPACKET_VERIFY);
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} else {
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} else {
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*lo_state = FPE_STATE_OFF;
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*lo_state = FPE_STATE_OFF;
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*lp_state = FPE_STATE_OFF;
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*lp_state = FPE_STATE_OFF;
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@ -5839,6 +5840,7 @@ static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
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/* If user has requested FPE enable, quickly response */
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/* If user has requested FPE enable, quickly response */
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if (*hs_enable)
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if (*hs_enable)
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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fpe_cfg,
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MPACKET_RESPONSE);
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MPACKET_RESPONSE);
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}
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}
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@ -7263,6 +7265,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work)
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if (*lo_state == FPE_STATE_ENTERING_ON &&
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if (*lo_state == FPE_STATE_ENTERING_ON &&
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*lp_state == FPE_STATE_ENTERING_ON) {
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*lp_state == FPE_STATE_ENTERING_ON) {
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stmmac_fpe_configure(priv, priv->ioaddr,
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stmmac_fpe_configure(priv, priv->ioaddr,
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fpe_cfg,
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priv->plat->tx_queues_to_use,
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priv->plat->tx_queues_to_use,
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priv->plat->rx_queues_to_use,
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priv->plat->rx_queues_to_use,
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*enable);
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*enable);
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@ -7281,6 +7284,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work)
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netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
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netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
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*lo_state, *lp_state);
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*lo_state, *lp_state);
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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fpe_cfg,
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MPACKET_VERIFY);
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MPACKET_VERIFY);
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}
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}
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/* Sleep then retry */
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/* Sleep then retry */
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@ -7295,6 +7299,7 @@ void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
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if (priv->plat->fpe_cfg->hs_enable != enable) {
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if (priv->plat->fpe_cfg->hs_enable != enable) {
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if (enable) {
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if (enable) {
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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stmmac_fpe_send_mpacket(priv, priv->ioaddr,
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priv->plat->fpe_cfg,
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MPACKET_VERIFY);
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MPACKET_VERIFY);
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} else {
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} else {
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priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
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priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
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@ -7755,6 +7760,7 @@ int stmmac_suspend(struct device *dev)
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if (priv->dma_cap.fpesel) {
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if (priv->dma_cap.fpesel) {
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/* Disable FPE */
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/* Disable FPE */
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stmmac_fpe_configure(priv, priv->ioaddr,
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stmmac_fpe_configure(priv, priv->ioaddr,
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priv->plat->fpe_cfg,
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priv->plat->tx_queues_to_use,
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priv->plat->tx_queues_to_use,
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priv->plat->rx_queues_to_use, false);
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priv->plat->rx_queues_to_use, false);
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@ -1079,6 +1079,7 @@ disable:
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priv->plat->fpe_cfg->enable = false;
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priv->plat->fpe_cfg->enable = false;
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stmmac_fpe_configure(priv, priv->ioaddr,
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stmmac_fpe_configure(priv, priv->ioaddr,
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priv->plat->fpe_cfg,
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priv->plat->tx_queues_to_use,
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priv->plat->tx_queues_to_use,
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priv->plat->rx_queues_to_use,
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priv->plat->rx_queues_to_use,
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false);
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false);
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@ -175,6 +175,7 @@ struct stmmac_fpe_cfg {
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bool hs_enable; /* FPE handshake enable */
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bool hs_enable; /* FPE handshake enable */
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enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
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enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
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enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
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enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
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u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
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};
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};
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struct stmmac_safety_feature_cfg {
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struct stmmac_safety_feature_cfg {
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