dt-bindings: msm: disp: add yaml schemas for DPU bindings
MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1621856653-10649-1-git-send-email-mkrishn@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Krishna Manikandan
Rob Clark
parent
c4681547bc
commit
3d7a0dd8f3
3 changed files with 440 additions and 141 deletions
228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
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228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
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@ -0,0 +1,228 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for SC7180 target
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maintainers:
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- Krishna Manikandan <mkrishn@codeaurora.org>
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description: |
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS and DPU are mentioned for SC7180 target.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-mdss
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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ranges: true
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interconnects:
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items:
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- description: Interconnect path specifying the port ids for data bus
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interconnect-names:
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const: mdp0-mem
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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description: Node containing the properties of DPU.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display hf axi clock
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- description: Display ahb clock
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- description: Display rotator clock
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- description: Display lut clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: bus
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- const: iface
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- const: rot
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- const: lut
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- const: core
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- const: vsync
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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operating-points-v2: true
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Contains the list of output ports from DPU device. These ports
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connect to interfaces that are external to the DPU hardware,
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such as DSI, DP etc. Each output port contains an endpoint that
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describes how it is connected to an external interface.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF1 (DSI1)
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF0 (DP)
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required:
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- port@0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- interrupts
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- power-domains
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- operating-points-v2
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- ports
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required:
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- compatible
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- reg
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- reg-names
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- power-domains
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- clocks
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- interrupts
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- interrupt-controller
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- iommus
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sc7180-mdss";
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reg = <0xae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "ahb", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
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interconnect-names = "mdp0-mem";
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iommus = <&apps_smmu 0x800 0x2>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sc7180-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus", "iface", "rot", "lut", "core",
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"vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&dp_in>;
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};
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};
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};
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};
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};
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...
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212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
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212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
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@ -0,0 +1,212 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for SDM845 target
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maintainers:
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- Krishna Manikandan <mkrishn@codeaurora.org>
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description: |
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS and DPU are mentioned for SDM845 target.
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properties:
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compatible:
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items:
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- const: qcom,sdm845-mdss
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AXI clock
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
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ranges: true
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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description: Node containing the properties of DPU.
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properties:
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compatible:
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items:
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- const: qcom,sdm845-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display ahb clock
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- description: Display axi clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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- const: vsync
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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operating-points-v2: true
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Contains the list of output ports from DPU device. These ports
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connect to interfaces that are external to the DPU hardware,
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such as DSI, DP etc. Each output port contains an endpoint that
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describes how it is connected to an external interface.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF1 (DSI1)
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF2 (DSI2)
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- interrupts
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- power-domains
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- operating-points-v2
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- ports
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required:
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- compatible
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- reg
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- reg-names
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- power-domains
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- clocks
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- interrupts
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- interrupt-controller
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- iommus
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sdm845-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x880 0x8>,
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<&apps_smmu 0xc80 0x8>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sdm845-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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||||||
|
clock-names = "iface", "bus", "core", "vsync";
|
||||||
|
|
||||||
|
interrupt-parent = <&mdss>;
|
||||||
|
interrupts = <0>;
|
||||||
|
power-domains = <&rpmhpd SDM845_CX>;
|
||||||
|
operating-points-v2 = <&mdp_opp_table>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
dpu_intf1_out: endpoint {
|
||||||
|
remote-endpoint = <&dsi0_in>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
dpu_intf2_out: endpoint {
|
||||||
|
remote-endpoint = <&dsi1_in>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
...
|
||||||
|
|
@ -1,141 +0,0 @@
|
||||||
Qualcomm Technologies, Inc. DPU KMS
|
|
||||||
|
|
||||||
Description:
|
|
||||||
|
|
||||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
|
||||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
|
||||||
The DPU display controller is found in SDM845 SoC.
|
|
||||||
|
|
||||||
MDSS:
|
|
||||||
Required properties:
|
|
||||||
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
|
|
||||||
- reg: physical base address and length of controller's registers.
|
|
||||||
- reg-names: register region names. The following region is required:
|
|
||||||
* "mdss"
|
|
||||||
- power-domains: a power domain consumer specifier according to
|
|
||||||
Documentation/devicetree/bindings/power/power_domain.txt
|
|
||||||
- clocks: list of clock specifiers for clocks needed by the device.
|
|
||||||
- clock-names: device clock names, must be in same order as clocks property.
|
|
||||||
The following clocks are required:
|
|
||||||
* "iface"
|
|
||||||
* "bus"
|
|
||||||
* "core"
|
|
||||||
- interrupts: interrupt signal from MDSS.
|
|
||||||
- interrupt-controller: identifies the node as an interrupt controller.
|
|
||||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
|
||||||
source, should be 1.
|
|
||||||
- iommus: phandle of iommu device node.
|
|
||||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
|
||||||
- #size-cells: Should be 1.
|
|
||||||
- ranges: parent bus address space is the same as the child bus address space.
|
|
||||||
- interconnects : interconnect path specifier for MDSS according to
|
|
||||||
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
|
|
||||||
2 paths corresponding to 2 AXI ports.
|
|
||||||
- interconnect-names : MDSS will have 2 port names to differentiate between the
|
|
||||||
2 interconnect paths defined with interconnect specifier.
|
|
||||||
|
|
||||||
Optional properties:
|
|
||||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
|
||||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
|
||||||
the assigned-clocks property.
|
|
||||||
|
|
||||||
MDP:
|
|
||||||
Required properties:
|
|
||||||
- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
|
|
||||||
- reg: physical base address and length of controller's registers.
|
|
||||||
- reg-names : register region names. The following region is required:
|
|
||||||
* "mdp"
|
|
||||||
* "vbif"
|
|
||||||
- clocks: list of clock specifiers for clocks needed by the device.
|
|
||||||
- clock-names: device clock names, must be in same order as clocks property.
|
|
||||||
The following clocks are required.
|
|
||||||
* "bus"
|
|
||||||
* "iface"
|
|
||||||
* "core"
|
|
||||||
* "vsync"
|
|
||||||
- interrupts: interrupt line from DPU to MDSS.
|
|
||||||
- ports: contains the list of output ports from DPU device. These ports connect
|
|
||||||
to interfaces that are external to the DPU hardware, such as DSI, DP etc.
|
|
||||||
|
|
||||||
Each output port contains an endpoint that describes how it is connected to an
|
|
||||||
external interface. These are described by the standard properties documented
|
|
||||||
here:
|
|
||||||
Documentation/devicetree/bindings/graph.txt
|
|
||||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
|
||||||
|
|
||||||
Port 0 -> DPU_INTF1 (DSI1)
|
|
||||||
Port 1 -> DPU_INTF2 (DSI2)
|
|
||||||
|
|
||||||
Optional properties:
|
|
||||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
|
||||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
|
||||||
the assigned-clocks property.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
mdss: mdss@ae00000 {
|
|
||||||
compatible = "qcom,sdm845-mdss";
|
|
||||||
reg = <0xae00000 0x1000>;
|
|
||||||
reg-names = "mdss";
|
|
||||||
|
|
||||||
power-domains = <&clock_dispcc 0>;
|
|
||||||
|
|
||||||
clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
|
|
||||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
|
||||||
clock-names = "iface", "bus", "core";
|
|
||||||
|
|
||||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
|
||||||
assigned-clock-rates = <300000000>;
|
|
||||||
|
|
||||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
|
|
||||||
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
|
|
||||||
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
|
|
||||||
|
|
||||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
|
||||||
|
|
||||||
iommus = <&apps_iommu 0>;
|
|
||||||
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0 0 0xae00000 0xb2008>;
|
|
||||||
|
|
||||||
mdss_mdp: mdp@ae01000 {
|
|
||||||
compatible = "qcom,sdm845-dpu";
|
|
||||||
reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
|
|
||||||
reg-names = "mdp", "vbif";
|
|
||||||
|
|
||||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
||||||
<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
|
|
||||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
||||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
||||||
clock-names = "iface", "bus", "core", "vsync";
|
|
||||||
|
|
||||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
||||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
||||||
assigned-clock-rates = <0 0 300000000 19200000>;
|
|
||||||
|
|
||||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
|
|
||||||
ports {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
port@0 {
|
|
||||||
reg = <0>;
|
|
||||||
dpu_intf1_out: endpoint {
|
|
||||||
remote-endpoint = <&dsi0_in>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
port@1 {
|
|
||||||
reg = <1>;
|
|
||||||
dpu_intf2_out: endpoint {
|
|
||||||
remote-endpoint = <&dsi1_in>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
Loading…
Add table
Reference in a new issue