ASoC: SOF: Intel: move common ATOM stuff to module
Split between ACPI/PCI parts and use common module. Since it's a split of existing code, the same dual-license is used for the new atom.c and atom.h files. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Bard Liao <bard.liao@intel.com> Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Tested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210505170235.306797-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pierre-Louis Bossart
Mark Brown
parent
1c5ab2dc75
commit
47fad2393b
5 changed files with 723 additions and 657 deletions
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@ -13,7 +13,10 @@ snd-sof-intel-hda-common-$(CONFIG_SND_SOC_SOF_HDA_PROBES) += hda-compress.o
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snd-sof-intel-hda-objs := hda-codec.o
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snd-sof-intel-hda-objs := hda-codec.o
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obj-$(CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP) += snd-sof-acpi-intel-byt.o
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snd-sof-intel-atom-objs := atom.o
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obj-$(CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP) += snd-sof-intel-atom.o
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obj-$(CONFIG_SND_SOC_SOF_BAYTRAIL) += snd-sof-acpi-intel-byt.o
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obj-$(CONFIG_SND_SOC_SOF_BROADWELL) += snd-sof-acpi-intel-bdw.o
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obj-$(CONFIG_SND_SOC_SOF_BROADWELL) += snd-sof-acpi-intel-bdw.o
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obj-$(CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC) += snd-sof-intel-ipc.o
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obj-$(CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC) += snd-sof-intel-ipc.o
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obj-$(CONFIG_SND_SOC_SOF_HDA_COMMON) += snd-sof-intel-hda-common.o
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obj-$(CONFIG_SND_SOC_SOF_HDA_COMMON) += snd-sof-intel-hda-common.o
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463
sound/soc/sof/intel/atom.c
Normal file
463
sound/soc/sof/intel/atom.c
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@ -0,0 +1,463 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
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//
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// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Atom devices
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*/
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#include <linux/module.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include <sound/soc-acpi.h>
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#include <sound/soc-acpi-intel-match.h>
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#include <sound/intel-dsp-config.h>
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#include "../ops.h"
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#include "shim.h"
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#include "atom.h"
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#include "../sof-acpi-dev.h"
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#include "../sof-audio.h"
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#include "../../intel/common/soc-intel-quirks.h"
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static void atom_host_done(struct snd_sof_dev *sdev);
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static void atom_dsp_done(struct snd_sof_dev *sdev);
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static void atom_get_reply(struct snd_sof_dev *sdev);
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/*
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* Debug
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*/
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static void atom_get_registers(struct snd_sof_dev *sdev,
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struct sof_ipc_dsp_oops_xtensa *xoops,
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struct sof_ipc_panic_info *panic_info,
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u32 *stack, size_t stack_words)
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{
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u32 offset = sdev->dsp_oops_offset;
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/* first read regsisters */
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sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
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/* note: variable AR register array is not read */
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/* then get panic info */
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if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
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dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
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xoops->arch_hdr.totalsize);
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return;
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}
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offset += xoops->arch_hdr.totalsize;
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sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
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/* then get the stack */
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offset += sizeof(*panic_info);
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sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
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}
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void atom_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[STACK_DUMP_SIZE];
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u64 status, panic, imrd, imrx;
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/* now try generic SOF status messages */
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status = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
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panic = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
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atom_get_registers(sdev, &xoops, &panic_info, stack,
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STACK_DUMP_SIZE);
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snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
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STACK_DUMP_SIZE);
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/* provide some context for firmware debug */
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imrx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRX);
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imrd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRD);
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dev_err(sdev->dev,
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"error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n",
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(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
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(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
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dev_err(sdev->dev,
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"error: mask host: pending %s complete %s raw 0x%llx\n",
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(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
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(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
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dev_err(sdev->dev,
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"error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n",
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(status & SHIM_IPCD_BUSY) ? "yes" : "no",
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(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
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dev_err(sdev->dev,
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"error: mask DSP: pending %s complete %s raw 0x%llx\n",
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(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
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(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
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}
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EXPORT_SYMBOL_NS(atom_dump, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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/*
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* IPC Doorbell IRQ handler and thread.
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*/
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irqreturn_t atom_irq_handler(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u64 ipcx, ipcd;
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int ret = IRQ_NONE;
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ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
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ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
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if (ipcx & SHIM_BYT_IPCX_DONE) {
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/* reply message from DSP, Mask Done interrupt first */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
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SHIM_IMRX,
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SHIM_IMRX_DONE,
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SHIM_IMRX_DONE);
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ret = IRQ_WAKE_THREAD;
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}
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if (ipcd & SHIM_BYT_IPCD_BUSY) {
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/* new message from DSP, Mask Busy interrupt first */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
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SHIM_IMRX,
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SHIM_IMRX_BUSY,
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SHIM_IMRX_BUSY);
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ret = IRQ_WAKE_THREAD;
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}
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return ret;
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}
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EXPORT_SYMBOL_NS(atom_irq_handler, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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irqreturn_t atom_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u64 ipcx, ipcd;
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ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
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ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
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/* reply message from DSP */
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if (ipcx & SHIM_BYT_IPCX_DONE) {
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spin_lock_irq(&sdev->ipc_lock);
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/*
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* handle immediate reply from DSP core. If the msg is
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* found, set done bit in cmd_done which is called at the
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* end of message processing function, else set it here
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* because the done bit can't be set in cmd_done function
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* which is triggered by msg
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*/
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atom_get_reply(sdev);
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snd_sof_ipc_reply(sdev, ipcx);
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atom_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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}
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/* new message from DSP */
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if (ipcd & SHIM_BYT_IPCD_BUSY) {
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/* Handle messages from DSP Core */
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if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(sdev, PANIC_OFFSET(ipcd) +
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MBOX_OFFSET);
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} else {
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snd_sof_ipc_msgs_rx(sdev);
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}
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atom_host_done(sdev);
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}
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_NS(atom_irq_thread, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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/* unmask and prepare to receive Done interrupt */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_DONE, 0);
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/* send the message */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write64(sdev, DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
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return 0;
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}
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EXPORT_SYMBOL_NS(atom_send_msg, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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static void atom_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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int ret = 0;
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/*
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* Sometimes, there is unexpected reply ipc arriving. The reply
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* ipc belongs to none of the ipcs sent from driver.
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* In this case, the driver must ignore the ipc.
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*/
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
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return;
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}
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/* get reply */
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sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply correct size ? */
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if (reply.hdr.size != msg->reply_size) {
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dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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sof_mailbox_read(sdev, sdev->host_box.offset,
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msg->reply_data, msg->reply_size);
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}
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msg->reply_error = ret;
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}
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int atom_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return MBOX_OFFSET;
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}
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EXPORT_SYMBOL_NS(atom_get_mailbox_offset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return MBOX_OFFSET;
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}
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EXPORT_SYMBOL_NS(atom_get_window_offset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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static void atom_host_done(struct snd_sof_dev *sdev)
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{
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/* clear BUSY bit and set DONE bit - accept new messages */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCD,
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SHIM_BYT_IPCD_BUSY |
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SHIM_BYT_IPCD_DONE,
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SHIM_BYT_IPCD_DONE);
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/* unmask and prepare to receive next new message */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_BUSY, 0);
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}
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static void atom_dsp_done(struct snd_sof_dev *sdev)
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{
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/* clear DONE bit - tell DSP we have completed */
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snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCX,
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SHIM_BYT_IPCX_DONE, 0);
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}
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/*
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* DSP control.
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*/
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int atom_run(struct snd_sof_dev *sdev)
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{
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int tries = 10;
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/* release stall and wait to unstall */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
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SHIM_BYT_CSR_STALL, 0x0);
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while (tries--) {
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if (!(snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_CSR) &
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SHIM_BYT_CSR_PWAITMODE))
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break;
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msleep(100);
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}
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if (tries < 0) {
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dev_err(sdev->dev, "error: unable to run DSP firmware\n");
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atom_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX);
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return -ENODEV;
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}
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/* return init core mask */
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return 1;
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}
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EXPORT_SYMBOL_NS(atom_run, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
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int atom_reset(struct snd_sof_dev *sdev)
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{
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/* put DSP into reset, set reset vector and stall */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
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SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
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SHIM_BYT_CSR_STALL,
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SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
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SHIM_BYT_CSR_STALL);
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usleep_range(10, 15);
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/* take DSP out of reset and keep stalled for FW loading */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
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SHIM_BYT_CSR_RST, 0);
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return 0;
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}
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||||||
|
EXPORT_SYMBOL_NS(atom_reset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
||||||
|
static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
|
||||||
|
const char *sof_tplg_filename,
|
||||||
|
const char *ssp_str)
|
||||||
|
{
|
||||||
|
const char *tplg_filename = NULL;
|
||||||
|
char *filename;
|
||||||
|
char *split_ext;
|
||||||
|
|
||||||
|
filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
|
||||||
|
if (!filename)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* this assumes a .tplg extension */
|
||||||
|
split_ext = strsep(&filename, ".");
|
||||||
|
if (split_ext) {
|
||||||
|
tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
|
||||||
|
"%s-%s.tplg",
|
||||||
|
split_ext, ssp_str);
|
||||||
|
if (!tplg_filename)
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
return tplg_filename;
|
||||||
|
}
|
||||||
|
|
||||||
|
void atom_machine_select(struct snd_sof_dev *sdev)
|
||||||
|
{
|
||||||
|
struct snd_sof_pdata *sof_pdata = sdev->pdata;
|
||||||
|
const struct sof_dev_desc *desc = sof_pdata->desc;
|
||||||
|
struct snd_soc_acpi_mach *mach;
|
||||||
|
struct platform_device *pdev;
|
||||||
|
const char *tplg_filename;
|
||||||
|
|
||||||
|
mach = snd_soc_acpi_find_machine(desc->machines);
|
||||||
|
if (!mach) {
|
||||||
|
dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
pdev = to_platform_device(sdev->dev);
|
||||||
|
if (soc_intel_is_byt_cr(pdev)) {
|
||||||
|
dev_dbg(sdev->dev,
|
||||||
|
"BYT-CR detected, SSP0 used instead of SSP2\n");
|
||||||
|
|
||||||
|
tplg_filename = fixup_tplg_name(sdev,
|
||||||
|
mach->sof_tplg_filename,
|
||||||
|
"ssp0");
|
||||||
|
} else {
|
||||||
|
tplg_filename = mach->sof_tplg_filename;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!tplg_filename) {
|
||||||
|
dev_dbg(sdev->dev,
|
||||||
|
"error: no topology filename\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
sof_pdata->tplg_filename = tplg_filename;
|
||||||
|
mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
|
||||||
|
sof_pdata->machine = mach;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_NS(atom_machine_select, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
||||||
|
/* Atom DAIs */
|
||||||
|
struct snd_soc_dai_driver atom_dai[] = {
|
||||||
|
{
|
||||||
|
.name = "ssp0-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = "ssp1-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = "ssp2-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = "ssp3-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = "ssp4-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = "ssp5-port",
|
||||||
|
.playback = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
.capture = {
|
||||||
|
.channels_min = 1,
|
||||||
|
.channels_max = 8,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
EXPORT_SYMBOL_NS(atom_dai, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
||||||
|
void atom_set_mach_params(const struct snd_soc_acpi_mach *mach,
|
||||||
|
struct snd_sof_dev *sdev)
|
||||||
|
{
|
||||||
|
struct snd_sof_pdata *pdata = sdev->pdata;
|
||||||
|
const struct sof_dev_desc *desc = pdata->desc;
|
||||||
|
struct snd_soc_acpi_mach_params *mach_params;
|
||||||
|
|
||||||
|
mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
|
||||||
|
mach_params->platform = dev_name(sdev->dev);
|
||||||
|
mach_params->num_dai_drivers = desc->ops->num_drv;
|
||||||
|
mach_params->dai_drivers = desc->ops->drv;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_NS(atom_set_mach_params, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
||||||
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
74
sound/soc/sof/intel/atom.h
Normal file
74
sound/soc/sof/intel/atom.h
Normal file
|
|
@ -0,0 +1,74 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
|
||||||
|
/*
|
||||||
|
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||||
|
* redistributing this file, you may do so under either license.
|
||||||
|
*
|
||||||
|
* Copyright(c) 2017-2021 Intel Corporation. All rights reserved.
|
||||||
|
*
|
||||||
|
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SOF_INTEL_ATOM_H
|
||||||
|
#define __SOF_INTEL_ATOM_H
|
||||||
|
|
||||||
|
/* DSP memories */
|
||||||
|
#define IRAM_OFFSET 0x0C0000
|
||||||
|
#define IRAM_SIZE (80 * 1024)
|
||||||
|
#define DRAM_OFFSET 0x100000
|
||||||
|
#define DRAM_SIZE (160 * 1024)
|
||||||
|
#define SHIM_OFFSET 0x140000
|
||||||
|
#define SHIM_SIZE_BYT 0x100
|
||||||
|
#define SHIM_SIZE_CHT 0x118
|
||||||
|
#define MBOX_OFFSET 0x144000
|
||||||
|
#define MBOX_SIZE 0x1000
|
||||||
|
#define EXCEPT_OFFSET 0x800
|
||||||
|
#define EXCEPT_MAX_HDR_SIZE 0x400
|
||||||
|
|
||||||
|
/* DSP peripherals */
|
||||||
|
#define DMAC0_OFFSET 0x098000
|
||||||
|
#define DMAC1_OFFSET 0x09c000
|
||||||
|
#define DMAC2_OFFSET 0x094000
|
||||||
|
#define DMAC_SIZE 0x420
|
||||||
|
#define SSP0_OFFSET 0x0a0000
|
||||||
|
#define SSP1_OFFSET 0x0a1000
|
||||||
|
#define SSP2_OFFSET 0x0a2000
|
||||||
|
#define SSP3_OFFSET 0x0a4000
|
||||||
|
#define SSP4_OFFSET 0x0a5000
|
||||||
|
#define SSP5_OFFSET 0x0a6000
|
||||||
|
#define SSP_SIZE 0x100
|
||||||
|
|
||||||
|
#define STACK_DUMP_SIZE 32
|
||||||
|
|
||||||
|
#define PCI_BAR_SIZE 0x200000
|
||||||
|
|
||||||
|
#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Debug
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define MBOX_DUMP_SIZE 0x30
|
||||||
|
|
||||||
|
/* BARs */
|
||||||
|
#define DSP_BAR 0
|
||||||
|
#define PCI_BAR 1
|
||||||
|
#define IMR_BAR 2
|
||||||
|
|
||||||
|
irqreturn_t atom_irq_handler(int irq, void *context);
|
||||||
|
irqreturn_t atom_irq_thread(int irq, void *context);
|
||||||
|
|
||||||
|
int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
|
||||||
|
int atom_get_mailbox_offset(struct snd_sof_dev *sdev);
|
||||||
|
int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id);
|
||||||
|
|
||||||
|
int atom_run(struct snd_sof_dev *sdev);
|
||||||
|
int atom_reset(struct snd_sof_dev *sdev);
|
||||||
|
void atom_dump(struct snd_sof_dev *sdev, u32 flags);
|
||||||
|
|
||||||
|
void atom_machine_select(struct snd_sof_dev *sdev);
|
||||||
|
void atom_set_mach_params(const struct snd_soc_acpi_mach *mach,
|
||||||
|
struct snd_sof_dev *sdev);
|
||||||
|
|
||||||
|
extern struct snd_soc_dai_driver atom_dai[];
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -19,54 +19,12 @@
|
||||||
#include <sound/soc-acpi-intel-match.h>
|
#include <sound/soc-acpi-intel-match.h>
|
||||||
#include <sound/intel-dsp-config.h>
|
#include <sound/intel-dsp-config.h>
|
||||||
#include "../ops.h"
|
#include "../ops.h"
|
||||||
|
#include "atom.h"
|
||||||
#include "shim.h"
|
#include "shim.h"
|
||||||
#include "../sof-acpi-dev.h"
|
#include "../sof-acpi-dev.h"
|
||||||
#include "../sof-audio.h"
|
#include "../sof-audio.h"
|
||||||
#include "../../intel/common/soc-intel-quirks.h"
|
#include "../../intel/common/soc-intel-quirks.h"
|
||||||
|
|
||||||
/* DSP memories */
|
|
||||||
#define IRAM_OFFSET 0x0C0000
|
|
||||||
#define IRAM_SIZE (80 * 1024)
|
|
||||||
#define DRAM_OFFSET 0x100000
|
|
||||||
#define DRAM_SIZE (160 * 1024)
|
|
||||||
#define SHIM_OFFSET 0x140000
|
|
||||||
#define SHIM_SIZE_BYT 0x100
|
|
||||||
#define SHIM_SIZE_CHT 0x118
|
|
||||||
#define MBOX_OFFSET 0x144000
|
|
||||||
#define MBOX_SIZE 0x1000
|
|
||||||
#define EXCEPT_OFFSET 0x800
|
|
||||||
#define EXCEPT_MAX_HDR_SIZE 0x400
|
|
||||||
|
|
||||||
/* DSP peripherals */
|
|
||||||
#define DMAC0_OFFSET 0x098000
|
|
||||||
#define DMAC1_OFFSET 0x09c000
|
|
||||||
#define DMAC2_OFFSET 0x094000
|
|
||||||
#define DMAC_SIZE 0x420
|
|
||||||
#define SSP0_OFFSET 0x0a0000
|
|
||||||
#define SSP1_OFFSET 0x0a1000
|
|
||||||
#define SSP2_OFFSET 0x0a2000
|
|
||||||
#define SSP3_OFFSET 0x0a4000
|
|
||||||
#define SSP4_OFFSET 0x0a5000
|
|
||||||
#define SSP5_OFFSET 0x0a6000
|
|
||||||
#define SSP_SIZE 0x100
|
|
||||||
|
|
||||||
#define STACK_DUMP_SIZE 32
|
|
||||||
|
|
||||||
#define PCI_BAR_SIZE 0x200000
|
|
||||||
|
|
||||||
#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Debug
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define MBOX_DUMP_SIZE 0x30
|
|
||||||
|
|
||||||
/* BARs */
|
|
||||||
#define DSP_BAR 0
|
|
||||||
#define PCI_BAR 1
|
|
||||||
#define IMR_BAR 2
|
|
||||||
|
|
||||||
static const struct snd_sof_debugfs_map byt_debugfs[] = {
|
static const struct snd_sof_debugfs_map byt_debugfs[] = {
|
||||||
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
|
@ -86,606 +44,33 @@ static const struct snd_sof_debugfs_map byt_debugfs[] = {
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct snd_sof_debugfs_map tng_debugfs[] = {
|
static const struct snd_sof_debugfs_map cht_debugfs[] = {
|
||||||
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
|
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
|
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
|
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
|
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
|
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
||||||
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
|
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
|
||||||
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
||||||
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
|
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
};
|
};
|
||||||
|
|
||||||
static void atom_host_done(struct snd_sof_dev *sdev);
|
|
||||||
static void atom_dsp_done(struct snd_sof_dev *sdev);
|
|
||||||
static void atom_get_reply(struct snd_sof_dev *sdev);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Debug
|
|
||||||
*/
|
|
||||||
|
|
||||||
static void atom_get_registers(struct snd_sof_dev *sdev,
|
|
||||||
struct sof_ipc_dsp_oops_xtensa *xoops,
|
|
||||||
struct sof_ipc_panic_info *panic_info,
|
|
||||||
u32 *stack, size_t stack_words)
|
|
||||||
{
|
|
||||||
u32 offset = sdev->dsp_oops_offset;
|
|
||||||
|
|
||||||
/* first read regsisters */
|
|
||||||
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
|
|
||||||
|
|
||||||
/* note: variable AR register array is not read */
|
|
||||||
|
|
||||||
/* then get panic info */
|
|
||||||
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
|
|
||||||
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
|
|
||||||
xoops->arch_hdr.totalsize);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
offset += xoops->arch_hdr.totalsize;
|
|
||||||
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
|
|
||||||
|
|
||||||
/* then get the stack */
|
|
||||||
offset += sizeof(*panic_info);
|
|
||||||
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
|
|
||||||
}
|
|
||||||
|
|
||||||
static void atom_dump(struct snd_sof_dev *sdev, u32 flags)
|
|
||||||
{
|
|
||||||
struct sof_ipc_dsp_oops_xtensa xoops;
|
|
||||||
struct sof_ipc_panic_info panic_info;
|
|
||||||
u32 stack[STACK_DUMP_SIZE];
|
|
||||||
u64 status, panic, imrd, imrx;
|
|
||||||
|
|
||||||
/* now try generic SOF status messages */
|
|
||||||
status = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
|
|
||||||
panic = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
|
|
||||||
atom_get_registers(sdev, &xoops, &panic_info, stack,
|
|
||||||
STACK_DUMP_SIZE);
|
|
||||||
snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
|
|
||||||
STACK_DUMP_SIZE);
|
|
||||||
|
|
||||||
/* provide some context for firmware debug */
|
|
||||||
imrx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRX);
|
|
||||||
imrd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRD);
|
|
||||||
dev_err(sdev->dev,
|
|
||||||
"error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n",
|
|
||||||
(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
|
|
||||||
(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
|
|
||||||
dev_err(sdev->dev,
|
|
||||||
"error: mask host: pending %s complete %s raw 0x%llx\n",
|
|
||||||
(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
|
|
||||||
(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
|
|
||||||
dev_err(sdev->dev,
|
|
||||||
"error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n",
|
|
||||||
(status & SHIM_IPCD_BUSY) ? "yes" : "no",
|
|
||||||
(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
|
|
||||||
dev_err(sdev->dev,
|
|
||||||
"error: mask DSP: pending %s complete %s raw 0x%llx\n",
|
|
||||||
(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
|
|
||||||
(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IPC Doorbell IRQ handler and thread.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static irqreturn_t atom_irq_handler(int irq, void *context)
|
|
||||||
{
|
|
||||||
struct snd_sof_dev *sdev = context;
|
|
||||||
u64 ipcx, ipcd;
|
|
||||||
int ret = IRQ_NONE;
|
|
||||||
|
|
||||||
ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
|
|
||||||
ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
|
|
||||||
|
|
||||||
if (ipcx & SHIM_BYT_IPCX_DONE) {
|
|
||||||
|
|
||||||
/* reply message from DSP, Mask Done interrupt first */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
|
|
||||||
SHIM_IMRX,
|
|
||||||
SHIM_IMRX_DONE,
|
|
||||||
SHIM_IMRX_DONE);
|
|
||||||
ret = IRQ_WAKE_THREAD;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (ipcd & SHIM_BYT_IPCD_BUSY) {
|
|
||||||
|
|
||||||
/* new message from DSP, Mask Busy interrupt first */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
|
|
||||||
SHIM_IMRX,
|
|
||||||
SHIM_IMRX_BUSY,
|
|
||||||
SHIM_IMRX_BUSY);
|
|
||||||
ret = IRQ_WAKE_THREAD;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t atom_irq_thread(int irq, void *context)
|
|
||||||
{
|
|
||||||
struct snd_sof_dev *sdev = context;
|
|
||||||
u64 ipcx, ipcd;
|
|
||||||
|
|
||||||
ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
|
|
||||||
ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
|
|
||||||
|
|
||||||
/* reply message from DSP */
|
|
||||||
if (ipcx & SHIM_BYT_IPCX_DONE) {
|
|
||||||
|
|
||||||
spin_lock_irq(&sdev->ipc_lock);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle immediate reply from DSP core. If the msg is
|
|
||||||
* found, set done bit in cmd_done which is called at the
|
|
||||||
* end of message processing function, else set it here
|
|
||||||
* because the done bit can't be set in cmd_done function
|
|
||||||
* which is triggered by msg
|
|
||||||
*/
|
|
||||||
atom_get_reply(sdev);
|
|
||||||
snd_sof_ipc_reply(sdev, ipcx);
|
|
||||||
|
|
||||||
atom_dsp_done(sdev);
|
|
||||||
|
|
||||||
spin_unlock_irq(&sdev->ipc_lock);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* new message from DSP */
|
|
||||||
if (ipcd & SHIM_BYT_IPCD_BUSY) {
|
|
||||||
|
|
||||||
/* Handle messages from DSP Core */
|
|
||||||
if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
|
|
||||||
snd_sof_dsp_panic(sdev, PANIC_OFFSET(ipcd) +
|
|
||||||
MBOX_OFFSET);
|
|
||||||
} else {
|
|
||||||
snd_sof_ipc_msgs_rx(sdev);
|
|
||||||
}
|
|
||||||
|
|
||||||
atom_host_done(sdev);
|
|
||||||
}
|
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
|
|
||||||
{
|
|
||||||
/* unmask and prepare to receive Done interrupt */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
|
|
||||||
SHIM_IMRX_DONE, 0);
|
|
||||||
|
|
||||||
/* send the message */
|
|
||||||
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
|
|
||||||
msg->msg_size);
|
|
||||||
snd_sof_dsp_write64(sdev, DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void atom_get_reply(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
struct snd_sof_ipc_msg *msg = sdev->msg;
|
|
||||||
struct sof_ipc_reply reply;
|
|
||||||
int ret = 0;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Sometimes, there is unexpected reply ipc arriving. The reply
|
|
||||||
* ipc belongs to none of the ipcs sent from driver.
|
|
||||||
* In this case, the driver must ignore the ipc.
|
|
||||||
*/
|
|
||||||
if (!msg) {
|
|
||||||
dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* get reply */
|
|
||||||
sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
|
|
||||||
|
|
||||||
if (reply.error < 0) {
|
|
||||||
memcpy(msg->reply_data, &reply, sizeof(reply));
|
|
||||||
ret = reply.error;
|
|
||||||
} else {
|
|
||||||
/* reply correct size ? */
|
|
||||||
if (reply.hdr.size != msg->reply_size) {
|
|
||||||
dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
|
|
||||||
msg->reply_size, reply.hdr.size);
|
|
||||||
ret = -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* read the message */
|
|
||||||
if (msg->reply_size > 0)
|
|
||||||
sof_mailbox_read(sdev, sdev->host_box.offset,
|
|
||||||
msg->reply_data, msg->reply_size);
|
|
||||||
}
|
|
||||||
|
|
||||||
msg->reply_error = ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int atom_get_mailbox_offset(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
return MBOX_OFFSET;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id)
|
|
||||||
{
|
|
||||||
return MBOX_OFFSET;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void atom_host_done(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
/* clear BUSY bit and set DONE bit - accept new messages */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCD,
|
|
||||||
SHIM_BYT_IPCD_BUSY |
|
|
||||||
SHIM_BYT_IPCD_DONE,
|
|
||||||
SHIM_BYT_IPCD_DONE);
|
|
||||||
|
|
||||||
/* unmask and prepare to receive next new message */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
|
|
||||||
SHIM_IMRX_BUSY, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void atom_dsp_done(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
/* clear DONE bit - tell DSP we have completed */
|
|
||||||
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCX,
|
|
||||||
SHIM_BYT_IPCX_DONE, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DSP control.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int atom_run(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
int tries = 10;
|
|
||||||
|
|
||||||
/* release stall and wait to unstall */
|
|
||||||
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
|
|
||||||
SHIM_BYT_CSR_STALL, 0x0);
|
|
||||||
while (tries--) {
|
|
||||||
if (!(snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_CSR) &
|
|
||||||
SHIM_BYT_CSR_PWAITMODE))
|
|
||||||
break;
|
|
||||||
msleep(100);
|
|
||||||
}
|
|
||||||
if (tries < 0) {
|
|
||||||
dev_err(sdev->dev, "error: unable to run DSP firmware\n");
|
|
||||||
atom_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* return init core mask */
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int atom_reset(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
/* put DSP into reset, set reset vector and stall */
|
|
||||||
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
|
|
||||||
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
|
|
||||||
SHIM_BYT_CSR_STALL,
|
|
||||||
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
|
|
||||||
SHIM_BYT_CSR_STALL);
|
|
||||||
|
|
||||||
usleep_range(10, 15);
|
|
||||||
|
|
||||||
/* take DSP out of reset and keep stalled for FW loading */
|
|
||||||
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
|
|
||||||
SHIM_BYT_CSR_RST, 0);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
|
|
||||||
const char *sof_tplg_filename,
|
|
||||||
const char *ssp_str)
|
|
||||||
{
|
|
||||||
const char *tplg_filename = NULL;
|
|
||||||
char *filename;
|
|
||||||
char *split_ext;
|
|
||||||
|
|
||||||
filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
|
|
||||||
if (!filename)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
/* this assumes a .tplg extension */
|
|
||||||
split_ext = strsep(&filename, ".");
|
|
||||||
if (split_ext) {
|
|
||||||
tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
|
|
||||||
"%s-%s.tplg",
|
|
||||||
split_ext, ssp_str);
|
|
||||||
if (!tplg_filename)
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
return tplg_filename;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void atom_machine_select(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
struct snd_sof_pdata *sof_pdata = sdev->pdata;
|
|
||||||
const struct sof_dev_desc *desc = sof_pdata->desc;
|
|
||||||
struct snd_soc_acpi_mach *mach;
|
|
||||||
struct platform_device *pdev;
|
|
||||||
const char *tplg_filename;
|
|
||||||
|
|
||||||
mach = snd_soc_acpi_find_machine(desc->machines);
|
|
||||||
if (!mach) {
|
|
||||||
dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
pdev = to_platform_device(sdev->dev);
|
|
||||||
if (soc_intel_is_byt_cr(pdev)) {
|
|
||||||
dev_dbg(sdev->dev,
|
|
||||||
"BYT-CR detected, SSP0 used instead of SSP2\n");
|
|
||||||
|
|
||||||
tplg_filename = fixup_tplg_name(sdev,
|
|
||||||
mach->sof_tplg_filename,
|
|
||||||
"ssp0");
|
|
||||||
} else {
|
|
||||||
tplg_filename = mach->sof_tplg_filename;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!tplg_filename) {
|
|
||||||
dev_dbg(sdev->dev,
|
|
||||||
"error: no topology filename\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
sof_pdata->tplg_filename = tplg_filename;
|
|
||||||
mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
|
|
||||||
sof_pdata->machine = mach;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Atom DAIs */
|
|
||||||
static struct snd_soc_dai_driver atom_dai[] = {
|
|
||||||
{
|
|
||||||
.name = "ssp0-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.name = "ssp1-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.name = "ssp2-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
}
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.name = "ssp3-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.name = "ssp4-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.name = "ssp5-port",
|
|
||||||
.playback = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
.capture = {
|
|
||||||
.channels_min = 1,
|
|
||||||
.channels_max = 8,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static void atom_set_mach_params(const struct snd_soc_acpi_mach *mach,
|
|
||||||
struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
struct snd_sof_pdata *pdata = sdev->pdata;
|
|
||||||
const struct sof_dev_desc *desc = pdata->desc;
|
|
||||||
struct snd_soc_acpi_mach_params *mach_params;
|
|
||||||
|
|
||||||
mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
|
|
||||||
mach_params->platform = dev_name(sdev->dev);
|
|
||||||
mach_params->num_dai_drivers = desc->ops->num_drv;
|
|
||||||
mach_params->dai_drivers = desc->ops->drv;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Probe and remove.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD)
|
|
||||||
|
|
||||||
static int tangier_pci_probe(struct snd_sof_dev *sdev)
|
|
||||||
{
|
|
||||||
struct snd_sof_pdata *pdata = sdev->pdata;
|
|
||||||
const struct sof_dev_desc *desc = pdata->desc;
|
|
||||||
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
|
||||||
u32 base, size;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
/* DSP DMA can only access low 31 bits of host memory */
|
|
||||||
ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
|
|
||||||
if (ret < 0) {
|
|
||||||
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* LPE base */
|
|
||||||
base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
|
|
||||||
size = PCI_BAR_SIZE;
|
|
||||||
|
|
||||||
dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
|
|
||||||
sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
|
|
||||||
if (!sdev->bar[DSP_BAR]) {
|
|
||||||
dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
|
|
||||||
base, size);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
|
|
||||||
|
|
||||||
/* IMR base - optional */
|
|
||||||
if (desc->resindex_imr_base == -1)
|
|
||||||
goto irq;
|
|
||||||
|
|
||||||
base = pci_resource_start(pci, desc->resindex_imr_base);
|
|
||||||
size = pci_resource_len(pci, desc->resindex_imr_base);
|
|
||||||
|
|
||||||
/* some BIOSes don't map IMR */
|
|
||||||
if (base == 0x55aa55aa || base == 0x0) {
|
|
||||||
dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
|
|
||||||
goto irq;
|
|
||||||
}
|
|
||||||
|
|
||||||
dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
|
|
||||||
sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
|
|
||||||
if (!sdev->bar[IMR_BAR]) {
|
|
||||||
dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
|
|
||||||
base, size);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
|
|
||||||
|
|
||||||
irq:
|
|
||||||
/* register our IRQ */
|
|
||||||
sdev->ipc_irq = pci->irq;
|
|
||||||
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
|
|
||||||
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
|
|
||||||
atom_irq_handler, atom_irq_thread,
|
|
||||||
0, "AudioDSP", sdev);
|
|
||||||
if (ret < 0) {
|
|
||||||
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
|
|
||||||
sdev->ipc_irq);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable BUSY and disable DONE Interrupt by default */
|
|
||||||
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
|
|
||||||
SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
|
|
||||||
SHIM_IMRX_DONE);
|
|
||||||
|
|
||||||
/* set default mailbox offset for FW ready message */
|
|
||||||
sdev->dsp_box.offset = MBOX_OFFSET;
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct snd_sof_dsp_ops sof_tng_ops = {
|
|
||||||
/* device init */
|
|
||||||
.probe = tangier_pci_probe,
|
|
||||||
|
|
||||||
/* DSP core boot / reset */
|
|
||||||
.run = atom_run,
|
|
||||||
.reset = atom_reset,
|
|
||||||
|
|
||||||
/* Register IO */
|
|
||||||
.write = sof_io_write,
|
|
||||||
.read = sof_io_read,
|
|
||||||
.write64 = sof_io_write64,
|
|
||||||
.read64 = sof_io_read64,
|
|
||||||
|
|
||||||
/* Block IO */
|
|
||||||
.block_read = sof_block_read,
|
|
||||||
.block_write = sof_block_write,
|
|
||||||
|
|
||||||
/* doorbell */
|
|
||||||
.irq_handler = atom_irq_handler,
|
|
||||||
.irq_thread = atom_irq_thread,
|
|
||||||
|
|
||||||
/* ipc */
|
|
||||||
.send_msg = atom_send_msg,
|
|
||||||
.fw_ready = sof_fw_ready,
|
|
||||||
.get_mailbox_offset = atom_get_mailbox_offset,
|
|
||||||
.get_window_offset = atom_get_window_offset,
|
|
||||||
|
|
||||||
.ipc_msg_data = intel_ipc_msg_data,
|
|
||||||
.ipc_pcm_params = intel_ipc_pcm_params,
|
|
||||||
|
|
||||||
/* machine driver */
|
|
||||||
.machine_select = atom_machine_select,
|
|
||||||
.machine_register = sof_machine_register,
|
|
||||||
.machine_unregister = sof_machine_unregister,
|
|
||||||
.set_mach_params = atom_set_mach_params,
|
|
||||||
|
|
||||||
/* debug */
|
|
||||||
.debug_map = tng_debugfs,
|
|
||||||
.debug_map_count = ARRAY_SIZE(tng_debugfs),
|
|
||||||
.dbg_dump = atom_dump,
|
|
||||||
|
|
||||||
/* stream callbacks */
|
|
||||||
.pcm_open = intel_pcm_open,
|
|
||||||
.pcm_close = intel_pcm_close,
|
|
||||||
|
|
||||||
/* module loading */
|
|
||||||
.load_module = snd_sof_parse_module_memcpy,
|
|
||||||
|
|
||||||
/*Firmware loading */
|
|
||||||
.load_firmware = snd_sof_load_firmware_memcpy,
|
|
||||||
|
|
||||||
/* DAI drivers */
|
|
||||||
.drv = atom_dai,
|
|
||||||
.num_drv = 3, /* we have only 3 SSPs on byt*/
|
|
||||||
|
|
||||||
/* ALSA HW info flags */
|
|
||||||
.hw_info = SNDRV_PCM_INFO_MMAP |
|
|
||||||
SNDRV_PCM_INFO_MMAP_VALID |
|
|
||||||
SNDRV_PCM_INFO_INTERLEAVED |
|
|
||||||
SNDRV_PCM_INFO_PAUSE |
|
|
||||||
SNDRV_PCM_INFO_BATCH,
|
|
||||||
|
|
||||||
.arch_ops = &sof_xtensa_arch_ops,
|
|
||||||
};
|
|
||||||
EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
|
|
||||||
|
|
||||||
const struct sof_intel_dsp_desc tng_chip_info = {
|
|
||||||
.cores_num = 1,
|
|
||||||
.host_managed_cores_mask = 1,
|
|
||||||
};
|
|
||||||
EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
|
|
||||||
|
|
||||||
#endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */
|
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
|
|
||||||
|
|
||||||
static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
|
static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
|
||||||
{
|
{
|
||||||
/* Disable Interrupt from both sides */
|
/* Disable Interrupt from both sides */
|
||||||
|
|
@ -722,33 +107,6 @@ static int byt_remove(struct snd_sof_dev *sdev)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct snd_sof_debugfs_map cht_debugfs[] = {
|
|
||||||
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
|
||||||
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
|
|
||||||
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
|
||||||
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
|
|
||||||
SOF_DEBUGFS_ACCESS_ALWAYS},
|
|
||||||
};
|
|
||||||
|
|
||||||
static int byt_acpi_probe(struct snd_sof_dev *sdev)
|
static int byt_acpi_probe(struct snd_sof_dev *sdev)
|
||||||
{
|
{
|
||||||
struct snd_sof_pdata *pdata = sdev->pdata;
|
struct snd_sof_pdata *pdata = sdev->pdata;
|
||||||
|
|
@ -1092,9 +450,8 @@ static struct platform_driver snd_sof_acpi_intel_byt_driver = {
|
||||||
};
|
};
|
||||||
module_platform_driver(snd_sof_acpi_intel_byt_driver);
|
module_platform_driver(snd_sof_acpi_intel_byt_driver);
|
||||||
|
|
||||||
#endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */
|
|
||||||
|
|
||||||
MODULE_LICENSE("Dual BSD/GPL");
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
|
||||||
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
||||||
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
|
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
|
||||||
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,10 @@
|
||||||
#include <sound/soc-acpi-intel-match.h>
|
#include <sound/soc-acpi-intel-match.h>
|
||||||
#include <sound/sof.h>
|
#include <sound/sof.h>
|
||||||
#include "../ops.h"
|
#include "../ops.h"
|
||||||
|
#include "atom.h"
|
||||||
|
#include "shim.h"
|
||||||
#include "../sof-pci-dev.h"
|
#include "../sof-pci-dev.h"
|
||||||
|
#include "../sof-audio.h"
|
||||||
|
|
||||||
/* platform specific devices */
|
/* platform specific devices */
|
||||||
#include "shim.h"
|
#include "shim.h"
|
||||||
|
|
@ -29,6 +32,170 @@ static struct snd_soc_acpi_mach sof_tng_machines[] = {
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct snd_sof_debugfs_map tng_debugfs[] = {
|
||||||
|
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
||||||
|
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
|
||||||
|
SOF_DEBUGFS_ACCESS_D0_ONLY},
|
||||||
|
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
|
||||||
|
SOF_DEBUGFS_ACCESS_ALWAYS},
|
||||||
|
};
|
||||||
|
|
||||||
|
static int tangier_pci_probe(struct snd_sof_dev *sdev)
|
||||||
|
{
|
||||||
|
struct snd_sof_pdata *pdata = sdev->pdata;
|
||||||
|
const struct sof_dev_desc *desc = pdata->desc;
|
||||||
|
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
||||||
|
u32 base, size;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* DSP DMA can only access low 31 bits of host memory */
|
||||||
|
ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* LPE base */
|
||||||
|
base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
|
||||||
|
size = PCI_BAR_SIZE;
|
||||||
|
|
||||||
|
dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
|
||||||
|
sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
|
||||||
|
if (!sdev->bar[DSP_BAR]) {
|
||||||
|
dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
|
||||||
|
base, size);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
|
||||||
|
|
||||||
|
/* IMR base - optional */
|
||||||
|
if (desc->resindex_imr_base == -1)
|
||||||
|
goto irq;
|
||||||
|
|
||||||
|
base = pci_resource_start(pci, desc->resindex_imr_base);
|
||||||
|
size = pci_resource_len(pci, desc->resindex_imr_base);
|
||||||
|
|
||||||
|
/* some BIOSes don't map IMR */
|
||||||
|
if (base == 0x55aa55aa || base == 0x0) {
|
||||||
|
dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
|
||||||
|
goto irq;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
|
||||||
|
sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
|
||||||
|
if (!sdev->bar[IMR_BAR]) {
|
||||||
|
dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
|
||||||
|
base, size);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
|
||||||
|
|
||||||
|
irq:
|
||||||
|
/* register our IRQ */
|
||||||
|
sdev->ipc_irq = pci->irq;
|
||||||
|
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
|
||||||
|
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
|
||||||
|
atom_irq_handler, atom_irq_thread,
|
||||||
|
0, "AudioDSP", sdev);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
|
||||||
|
sdev->ipc_irq);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable BUSY and disable DONE Interrupt by default */
|
||||||
|
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
|
||||||
|
SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
|
||||||
|
SHIM_IMRX_DONE);
|
||||||
|
|
||||||
|
/* set default mailbox offset for FW ready message */
|
||||||
|
sdev->dsp_box.offset = MBOX_OFFSET;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct snd_sof_dsp_ops sof_tng_ops = {
|
||||||
|
/* device init */
|
||||||
|
.probe = tangier_pci_probe,
|
||||||
|
|
||||||
|
/* DSP core boot / reset */
|
||||||
|
.run = atom_run,
|
||||||
|
.reset = atom_reset,
|
||||||
|
|
||||||
|
/* Register IO */
|
||||||
|
.write = sof_io_write,
|
||||||
|
.read = sof_io_read,
|
||||||
|
.write64 = sof_io_write64,
|
||||||
|
.read64 = sof_io_read64,
|
||||||
|
|
||||||
|
/* Block IO */
|
||||||
|
.block_read = sof_block_read,
|
||||||
|
.block_write = sof_block_write,
|
||||||
|
|
||||||
|
/* doorbell */
|
||||||
|
.irq_handler = atom_irq_handler,
|
||||||
|
.irq_thread = atom_irq_thread,
|
||||||
|
|
||||||
|
/* ipc */
|
||||||
|
.send_msg = atom_send_msg,
|
||||||
|
.fw_ready = sof_fw_ready,
|
||||||
|
.get_mailbox_offset = atom_get_mailbox_offset,
|
||||||
|
.get_window_offset = atom_get_window_offset,
|
||||||
|
|
||||||
|
.ipc_msg_data = intel_ipc_msg_data,
|
||||||
|
.ipc_pcm_params = intel_ipc_pcm_params,
|
||||||
|
|
||||||
|
/* machine driver */
|
||||||
|
.machine_select = atom_machine_select,
|
||||||
|
.machine_register = sof_machine_register,
|
||||||
|
.machine_unregister = sof_machine_unregister,
|
||||||
|
.set_mach_params = atom_set_mach_params,
|
||||||
|
|
||||||
|
/* debug */
|
||||||
|
.debug_map = tng_debugfs,
|
||||||
|
.debug_map_count = ARRAY_SIZE(tng_debugfs),
|
||||||
|
.dbg_dump = atom_dump,
|
||||||
|
|
||||||
|
/* stream callbacks */
|
||||||
|
.pcm_open = intel_pcm_open,
|
||||||
|
.pcm_close = intel_pcm_close,
|
||||||
|
|
||||||
|
/* module loading */
|
||||||
|
.load_module = snd_sof_parse_module_memcpy,
|
||||||
|
|
||||||
|
/*Firmware loading */
|
||||||
|
.load_firmware = snd_sof_load_firmware_memcpy,
|
||||||
|
|
||||||
|
/* DAI drivers */
|
||||||
|
.drv = atom_dai,
|
||||||
|
.num_drv = 3, /* we have only 3 SSPs on byt*/
|
||||||
|
|
||||||
|
/* ALSA HW info flags */
|
||||||
|
.hw_info = SNDRV_PCM_INFO_MMAP |
|
||||||
|
SNDRV_PCM_INFO_MMAP_VALID |
|
||||||
|
SNDRV_PCM_INFO_INTERLEAVED |
|
||||||
|
SNDRV_PCM_INFO_PAUSE |
|
||||||
|
SNDRV_PCM_INFO_BATCH,
|
||||||
|
|
||||||
|
.arch_ops = &sof_xtensa_arch_ops,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct sof_intel_dsp_desc tng_chip_info = {
|
||||||
|
.cores_num = 1,
|
||||||
|
.host_managed_cores_mask = 1,
|
||||||
|
};
|
||||||
|
|
||||||
static const struct sof_dev_desc tng_desc = {
|
static const struct sof_dev_desc tng_desc = {
|
||||||
.machines = sof_tng_machines,
|
.machines = sof_tng_machines,
|
||||||
.resindex_lpe_base = 3, /* IRAM, but subtract IRAM offset */
|
.resindex_lpe_base = 3, /* IRAM, but subtract IRAM offset */
|
||||||
|
|
@ -66,5 +233,7 @@ static struct pci_driver snd_sof_pci_intel_tng_driver = {
|
||||||
module_pci_driver(snd_sof_pci_intel_tng_driver);
|
module_pci_driver(snd_sof_pci_intel_tng_driver);
|
||||||
|
|
||||||
MODULE_LICENSE("Dual BSD/GPL");
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
MODULE_IMPORT_NS(SND_SOC_SOF_MERRIFIELD);
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
|
||||||
|
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
||||||
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
|
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
|
||||||
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue