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drm/amd/display: Re-enable DPP/HUBP Power Gating

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[Why & How]
Bugs preventing DPP/HUBP power gating have been addressed
so this should be reenabled on dcn314 for sufficient
hardware rev versions

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Daniel Miess 2023-05-23 14:21:59 -04:00 • committed by Alex Deucher
parent 1c982c9ffe
commit 4cc1cebe08
1 changed files with 9 additions and 2 deletions
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11
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
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@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_dpp_power_gate = true,
.disable_hubp_power_gate = true,
.disable_dpp_power_gate = false,
.disable_hubp_power_gate = false,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = false,
@ -1883,6 +1883,13 @@ static bool dcn314_resource_construct(
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;
/* Disable pipe power gating when unsupported */
if (ctx->asic_id.hw_internal_rev == 0x01 ||
ctx->asic_id.hw_internal_rev == 0x80) {
dc->debug.disable_dpp_power_gate = true;
dc->debug.disable_hubp_power_gate = true;
}
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {