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arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM

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In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for
uart5 cannot be used for the UART CTS/RTS, because they are already
allocated for different purposes. CTS pin is routed to SUS_S3#
signal, while RTS pin is used internally and is not available on
Q7 connector. Move definition of the pinctrl-0 property from
px30-ringneck-haikou.dts to px30-ringneck.dtsi.

This commit is a dependency to next commit in the patch series,
that disables DMA for uart5.

Cc: stable@vger.kernel.org
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Lukasz Czechowski 2025-01-21 13:56:03 +01:00 • committed by Heiko Stuebner
parent a6a7cba17c
commit 4eee627ea5
2 changed files with 4 additions and 1 deletions
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1
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
View file

@ -226,7 +226,6 @@
};
&uart5 {
pinctrl-0 = <&uart5_xfer>;
rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
View file

@ -396,6 +396,10 @@
status = "okay";
};
&uart5 {
pinctrl-0 = <&uart5_xfer>;
};
/* Mule UCAN */
&usb_host0_ehci {
status = "okay";