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x86/msr: Move ARCH_CAP_XAPIC_DISABLE bit definition to its rightful place

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The ARCH_CAP_XAPIC_DISABLE bit of MSR_IA32_ARCH_CAP is not in the
correct sorted order. Move it where it belongs.

No functional change.

  [ bp: Massage commit message. ]

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/243317ff6c8db307b7701a45f71e5c21da80194b.1705632532.git.pawan.kumar.gupta@linux.intel.com
This commit is contained in:
Pawan Gupta 2024-01-18 18:52:24 -08:00 • committed by Borislav Petkov (AMD)
parent e0ca9353a8
commit 53bc516ade
1 changed files with 4 additions and 5 deletions
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9
arch/x86/include/asm/msr-index.h
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@ -163,6 +163,10 @@
* are restricted to targets in * are restricted to targets in
* kernel. * kernel.
*/ */
#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
* IA32_XAPIC_DISABLE_STATUS MSR
* supported
*/
#define ARCH_CAP_PBRSB_NO BIT(24) /* #define ARCH_CAP_PBRSB_NO BIT(24) /*
* Not susceptible to Post-Barrier * Not susceptible to Post-Barrier
* Return Stack Buffer Predictions. * Return Stack Buffer Predictions.
@ -185,11 +189,6 @@
* File. * File.
*/ */
#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
* IA32_XAPIC_DISABLE_STATUS MSR
* supported
*/
#define MSR_IA32_FLUSH_CMD 0x0000010b #define MSR_IA32_FLUSH_CMD 0x0000010b
#define L1D_FLUSH BIT(0) /* #define L1D_FLUSH BIT(0) /*
* Writeback and invalidate the * Writeback and invalidate the