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x86/srso: Tie SBPB bit setting to microcode patch detection

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The SBPB bit in MSR_IA32_PRED_CMD is supported only after a microcode
patch has been applied so set X86_FEATURE_SBPB only then. Otherwise,
guests would attempt to set that bit and #GP on the MSR write.

While at it, make SMT detection more robust as some guests - depending
on how and what CPUID leafs their report - lead to cpu_smt_control
getting set to CPU_SMT_NOT_SUPPORTED but SRSO_NO should be set for any
guest incarnation where one simply cannot do SMT, for whatever reason.

Fixes: fb3bd914b3 ("x86/srso: Add a Speculative RAS Overflow mitigation")
Reported-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reported-by: Salvatore Bonaccorso <carnil@debian.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
This commit is contained in:
Borislav Petkov (AMD) 2023-08-07 10:46:04 +02:00
parent 3bbbe97ad8
commit 5a15d83488
2 changed files with 15 additions and 11 deletions
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17
arch/x86/kernel/cpu/amd.c
View file

@ -1238,14 +1238,19 @@ EXPORT_SYMBOL_GPL(amd_get_highest_perf);
bool cpu_has_ibpb_brtype_microcode(void) bool cpu_has_ibpb_brtype_microcode(void)
{ {
u8 fam = boot_cpu_data.x86; switch (boot_cpu_data.x86) {
/* Zen1/2 IBPB flushes branch type predictions too. */ /* Zen1/2 IBPB flushes branch type predictions too. */
if (fam == 0x17) case 0x17:
return boot_cpu_has(X86_FEATURE_AMD_IBPB); return boot_cpu_has(X86_FEATURE_AMD_IBPB);
case 0x19:
/* Poke the MSR bit on Zen3/4 to check its presence. */ /* Poke the MSR bit on Zen3/4 to check its presence. */
else if (fam == 0x19) if (!wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
return !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB); setup_force_cpu_cap(X86_FEATURE_SBPB);
else return true;
} else {
return false; return false;
} }
default:
return false;
}
}

7
arch/x86/kernel/cpu/bugs.c
View file

@ -2265,14 +2265,13 @@ static void __init srso_select_mitigation(void)
* flags for guests. * flags for guests.
*/ */
setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
setup_force_cpu_cap(X86_FEATURE_SBPB);
/* /*
* Zen1/2 with SMT off aren't vulnerable after the right * Zen1/2 with SMT off aren't vulnerable after the right
* IBPB microcode has been applied. * IBPB microcode has been applied.
*/ */
if ((boot_cpu_data.x86 < 0x19) && if ((boot_cpu_data.x86 < 0x19) &&
(cpu_smt_control == CPU_SMT_DISABLED)) (!cpu_smt_possible() || (cpu_smt_control == CPU_SMT_DISABLED)))
setup_force_cpu_cap(X86_FEATURE_SRSO_NO); setup_force_cpu_cap(X86_FEATURE_SRSO_NO);
} }
@ -2345,8 +2344,8 @@ static void __init srso_select_mitigation(void)
pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode")); pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode"));
pred_cmd: pred_cmd:
if (boot_cpu_has(X86_FEATURE_SRSO_NO) || if ((boot_cpu_has(X86_FEATURE_SRSO_NO) || srso_cmd == SRSO_CMD_OFF) &&
srso_cmd == SRSO_CMD_OFF) boot_cpu_has(X86_FEATURE_SBPB))
x86_pred_cmd = PRED_CMD_SBPB; x86_pred_cmd = PRED_CMD_SBPB;
} }