drm/amdgpu: add selftest framework for UMSCH
Prepare for VPE and VCN queue submission test. v2: rebase on drm_exec (Alex) Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lang Yu
Alex Deucher
parent
dc6f3d6ff2
commit
5d5eac7e83
1 changed files with 404 additions and 1 deletions
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@ -23,11 +23,412 @@
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*/
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#include <linux/firmware.h>
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#include <drm/drm_exec.h>
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#include "amdgpu.h"
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#include "amdgpu_umsch_mm.h"
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#include "umsch_mm_v4_0.h"
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struct umsch_mm_test_ctx_data {
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uint8_t process_csa[PAGE_SIZE];
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uint8_t vpe_ctx_csa[PAGE_SIZE];
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uint8_t vcn_ctx_csa[PAGE_SIZE];
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};
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struct umsch_mm_test_mqd_data {
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uint8_t vpe_mqd[PAGE_SIZE];
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uint8_t vcn_mqd[PAGE_SIZE];
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};
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struct umsch_mm_test_ring_data {
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uint8_t vpe_ring[PAGE_SIZE];
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uint8_t vpe_ib[PAGE_SIZE];
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uint8_t vcn_ring[PAGE_SIZE];
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uint8_t vcn_ib[PAGE_SIZE];
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};
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struct umsch_mm_test_queue_info {
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uint64_t mqd_addr;
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uint64_t csa_addr;
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uint32_t doorbell_offset_0;
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uint32_t doorbell_offset_1;
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enum UMSCH_SWIP_ENGINE_TYPE engine;
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};
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struct umsch_mm_test {
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struct amdgpu_bo *ctx_data_obj;
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uint64_t ctx_data_gpu_addr;
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uint32_t *ctx_data_cpu_addr;
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struct amdgpu_bo *mqd_data_obj;
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uint64_t mqd_data_gpu_addr;
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uint32_t *mqd_data_cpu_addr;
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struct amdgpu_bo *ring_data_obj;
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uint64_t ring_data_gpu_addr;
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uint32_t *ring_data_cpu_addr;
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struct amdgpu_vm *vm;
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struct amdgpu_bo_va *bo_va;
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uint32_t pasid;
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uint32_t vm_cntx_cntl;
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uint32_t num_queues;
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};
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static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
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uint64_t addr, uint32_t size)
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{
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struct amdgpu_sync sync;
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struct drm_exec exec;
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int r;
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amdgpu_sync_create(&sync);
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drm_exec_init(&exec, 0);
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drm_exec_until_all_locked(&exec) {
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r = drm_exec_lock_obj(&exec, &bo->tbo.base);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto error_fini_exec;
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r = amdgpu_vm_lock_pd(vm, &exec, 0);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto error_fini_exec;
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}
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*bo_va = amdgpu_vm_bo_add(adev, vm, bo);
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if (!*bo_va) {
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r = -ENOMEM;
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goto error_fini_exec;
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}
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r = amdgpu_vm_bo_map(adev, *bo_va, addr, 0, size,
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AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
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AMDGPU_PTE_EXECUTABLE);
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if (r)
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goto error_del_bo_va;
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r = amdgpu_vm_bo_update(adev, *bo_va, false);
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if (r)
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goto error_del_bo_va;
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amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update);
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r = amdgpu_vm_update_pdes(adev, vm, false);
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if (r)
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goto error_del_bo_va;
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amdgpu_sync_fence(&sync, vm->last_update);
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amdgpu_sync_wait(&sync, false);
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drm_exec_fini(&exec);
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amdgpu_sync_free(&sync);
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return 0;
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error_del_bo_va:
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amdgpu_vm_bo_del(adev, *bo_va);
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amdgpu_sync_free(&sync);
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error_fini_exec:
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drm_exec_fini(&exec);
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amdgpu_sync_free(&sync);
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return r;
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}
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static int unmap_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo *bo, struct amdgpu_bo_va *bo_va,
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uint64_t addr)
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{
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struct drm_exec exec;
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long r;
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drm_exec_init(&exec, 0);
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drm_exec_until_all_locked(&exec) {
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r = drm_exec_lock_obj(&exec, &bo->tbo.base);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto out_unlock;
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r = amdgpu_vm_lock_pd(vm, &exec, 0);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto out_unlock;
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}
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r = amdgpu_vm_bo_unmap(adev, bo_va, addr);
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if (r)
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goto out_unlock;
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amdgpu_vm_bo_del(adev, bo_va);
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out_unlock:
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drm_exec_fini(&exec);
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return r;
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}
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static void setup_vpe_queue(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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}
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static void setup_vcn_queue(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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}
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static int add_test_queue(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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struct umsch_mm_add_queue_input queue_input = {};
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int r;
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queue_input.process_id = test->pasid;
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queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(test->vm->root.bo);
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queue_input.process_va_start = 0;
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queue_input.process_va_end = (adev->vm_manager.max_pfn - 1) << AMDGPU_GPU_PAGE_SHIFT;
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queue_input.process_quantum = 100000; /* 10ms */
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queue_input.process_csa_addr = test->ctx_data_gpu_addr +
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offsetof(struct umsch_mm_test_ctx_data, process_csa);
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queue_input.context_quantum = 10000; /* 1ms */
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queue_input.context_csa_addr = qinfo->csa_addr;
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queue_input.inprocess_context_priority = CONTEXT_PRIORITY_LEVEL_NORMAL;
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queue_input.context_global_priority_level = CONTEXT_PRIORITY_LEVEL_NORMAL;
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queue_input.doorbell_offset_0 = qinfo->doorbell_offset_0;
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queue_input.doorbell_offset_1 = qinfo->doorbell_offset_1;
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queue_input.engine_type = qinfo->engine;
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queue_input.mqd_addr = qinfo->mqd_addr;
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queue_input.vm_context_cntl = test->vm_cntx_cntl;
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amdgpu_umsch_mm_lock(&adev->umsch_mm);
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r = adev->umsch_mm.funcs->add_queue(&adev->umsch_mm, &queue_input);
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amdgpu_umsch_mm_unlock(&adev->umsch_mm);
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if (r)
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return r;
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return 0;
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}
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static int remove_test_queue(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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struct umsch_mm_remove_queue_input queue_input = {};
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int r;
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queue_input.doorbell_offset_0 = qinfo->doorbell_offset_0;
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queue_input.doorbell_offset_1 = qinfo->doorbell_offset_1;
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queue_input.context_csa_addr = qinfo->csa_addr;
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amdgpu_umsch_mm_lock(&adev->umsch_mm);
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r = adev->umsch_mm.funcs->remove_queue(&adev->umsch_mm, &queue_input);
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amdgpu_umsch_mm_unlock(&adev->umsch_mm);
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if (r)
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return r;
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return 0;
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}
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static int submit_vpe_queue(struct amdgpu_device *adev, struct umsch_mm_test *test)
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{
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return 0;
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}
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static int submit_vcn_queue(struct amdgpu_device *adev, struct umsch_mm_test *test)
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{
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return 0;
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}
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static int setup_umsch_mm_test(struct amdgpu_device *adev,
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struct umsch_mm_test *test)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
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int r;
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test->vm_cntx_cntl = hub->vm_cntx_cntl;
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test->vm = kzalloc(sizeof(*test->vm), GFP_KERNEL);
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if (!test->vm) {
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r = -ENOMEM;
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return r;
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}
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r = amdgpu_vm_init(adev, test->vm, -1);
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if (r)
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goto error_free_vm;
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test->pasid = amdgpu_pasid_alloc(16);
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if (test->pasid < 0) {
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r = test->pasid;
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goto error_fini_vm;
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}
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r = amdgpu_bo_create_kernel(adev, sizeof(struct umsch_mm_test_ctx_data),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&test->ctx_data_obj,
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&test->ctx_data_gpu_addr,
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(void **)&test->ctx_data_cpu_addr);
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if (r)
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goto error_free_pasid;
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memset(test->ctx_data_cpu_addr, 0, sizeof(struct umsch_mm_test_ctx_data));
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&test->mqd_data_obj,
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&test->mqd_data_gpu_addr,
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(void **)&test->mqd_data_cpu_addr);
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if (r)
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goto error_free_ctx_data_obj;
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memset(test->mqd_data_cpu_addr, 0, PAGE_SIZE);
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r = amdgpu_bo_create_kernel(adev, sizeof(struct umsch_mm_test_ring_data),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&test->ring_data_obj,
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NULL,
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(void **)&test->ring_data_cpu_addr);
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if (r)
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goto error_free_mqd_data_obj;
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memset(test->ring_data_cpu_addr, 0, sizeof(struct umsch_mm_test_ring_data));
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test->ring_data_gpu_addr = AMDGPU_VA_RESERVED_SIZE;
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r = map_ring_data(adev, test->vm, test->ring_data_obj, &test->bo_va,
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test->ring_data_gpu_addr, sizeof(struct umsch_mm_test_ring_data));
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if (r)
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goto error_free_ring_data_obj;
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return 0;
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error_free_ring_data_obj:
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amdgpu_bo_free_kernel(&test->ring_data_obj, NULL,
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(void **)&test->ring_data_cpu_addr);
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error_free_mqd_data_obj:
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amdgpu_bo_free_kernel(&test->mqd_data_obj, &test->mqd_data_gpu_addr,
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(void **)&test->mqd_data_cpu_addr);
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error_free_ctx_data_obj:
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amdgpu_bo_free_kernel(&test->ctx_data_obj, &test->ctx_data_gpu_addr,
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(void **)&test->ctx_data_cpu_addr);
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error_free_pasid:
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amdgpu_pasid_free(test->pasid);
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error_fini_vm:
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amdgpu_vm_fini(adev, test->vm);
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error_free_vm:
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kfree(test->vm);
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return r;
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}
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static void cleanup_umsch_mm_test(struct amdgpu_device *adev,
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struct umsch_mm_test *test)
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{
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unmap_ring_data(adev, test->vm, test->ring_data_obj,
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test->bo_va, test->ring_data_gpu_addr);
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amdgpu_bo_free_kernel(&test->mqd_data_obj, &test->mqd_data_gpu_addr,
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(void **)&test->mqd_data_cpu_addr);
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amdgpu_bo_free_kernel(&test->ring_data_obj, NULL,
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(void **)&test->ring_data_cpu_addr);
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amdgpu_bo_free_kernel(&test->ctx_data_obj, &test->ctx_data_gpu_addr,
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(void **)&test->ctx_data_cpu_addr);
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amdgpu_pasid_free(test->pasid);
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amdgpu_vm_fini(adev, test->vm);
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kfree(test->vm);
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}
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static int setup_test_queues(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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int i, r;
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for (i = 0; i < test->num_queues; i++) {
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if (qinfo[i].engine == UMSCH_SWIP_ENGINE_TYPE_VPE)
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setup_vpe_queue(adev, test, &qinfo[i]);
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else
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setup_vcn_queue(adev, test, &qinfo[i]);
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r = add_test_queue(adev, test, &qinfo[i]);
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if (r)
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return r;
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}
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return 0;
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}
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static int submit_test_queues(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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int i, r;
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for (i = 0; i < test->num_queues; i++) {
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if (qinfo[i].engine == UMSCH_SWIP_ENGINE_TYPE_VPE)
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r = submit_vpe_queue(adev, test);
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else
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r = submit_vcn_queue(adev, test);
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if (r)
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return r;
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}
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return 0;
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}
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static void cleanup_test_queues(struct amdgpu_device *adev,
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struct umsch_mm_test *test,
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struct umsch_mm_test_queue_info *qinfo)
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{
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int i;
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for (i = 0; i < test->num_queues; i++)
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remove_test_queue(adev, test, &qinfo[i]);
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}
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static int umsch_mm_test(struct amdgpu_device *adev)
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{
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struct umsch_mm_test_queue_info qinfo[] = {};
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struct umsch_mm_test test = { .num_queues = ARRAY_SIZE(qinfo) };
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int r;
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r = setup_umsch_mm_test(adev, &test);
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if (r)
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return r;
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r = setup_test_queues(adev, &test, qinfo);
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if (r)
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goto cleanup;
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r = submit_test_queues(adev, &test, qinfo);
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if (r)
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goto cleanup;
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cleanup_test_queues(adev, &test, qinfo);
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cleanup_umsch_mm_test(adev, &test);
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return 0;
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cleanup:
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cleanup_test_queues(adev, &test, qinfo);
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cleanup_umsch_mm_test(adev, &test);
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return r;
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}
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int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws)
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{
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struct amdgpu_ring *ring = &umsch->ring;
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@ -272,7 +673,9 @@ static int umsch_mm_early_init(void *handle)
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static int umsch_mm_late_init(void *handle)
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{
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return 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return umsch_mm_test(adev);
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}
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static int umsch_mm_sw_init(void *handle)
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