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drm/i915: Identify Cometlake platform

Browse source 
Cometlake is a small refresh of Coffeelake, but since we have found out a
difference in the plaforms, we need to identify them as separate platforms.

Since we previously took Coffeelake/Cometlake as identical, update all
IS_COFFEELAKE() to also include IS_COMETLAKE().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200602140541.5481-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2020-06-02 15:05:40 +01:00
parent c95ebab1c7
commit 5f4ae2704d
15 changed files with 140 additions and 55 deletions
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4
drivers/gpu/drm/i915/display/intel_csr.c
View file

@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
csr->fw_path = GLK_CSR_PATH; csr->fw_path = GLK_CSR_PATH;
csr->required_version = GLK_CSR_VERSION_REQUIRED; csr->required_version = GLK_CSR_VERSION_REQUIRED;
csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { } else if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
csr->fw_path = KBL_CSR_PATH; csr->fw_path = KBL_CSR_PATH;
csr->required_version = KBL_CSR_VERSION_REQUIRED; csr->required_version = KBL_CSR_VERSION_REQUIRED;
csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;

34
drivers/gpu/drm/i915/display/intel_ddi.c
View file

@ -722,10 +722,14 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
static const struct ddi_buf_trans * static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
{ {
if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { if (IS_KBL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv) ||
IS_CML_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
return kbl_y_ddi_translations_dp; return kbl_y_ddi_translations_dp;
} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { } else if (IS_KBL_ULT(dev_priv) ||
IS_CFL_ULT(dev_priv) ||
IS_CML_ULT(dev_priv)) {
*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
return kbl_u_ddi_translations_dp; return kbl_u_ddi_translations_dp;
} else { } else {
@ -738,12 +742,16 @@ static const struct ddi_buf_trans *
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{ {
if (dev_priv->vbt.edp.low_vswing) { if (dev_priv->vbt.edp.low_vswing) {
if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || if (IS_SKL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv)) { IS_KBL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv) ||
IS_CML_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
return skl_y_ddi_translations_edp; return skl_y_ddi_translations_edp;
} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || } else if (IS_SKL_ULT(dev_priv) ||
IS_CFL_ULT(dev_priv)) { IS_KBL_ULT(dev_priv) ||
IS_CFL_ULT(dev_priv) ||
IS_CML_ULT(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
return skl_u_ddi_translations_edp; return skl_u_ddi_translations_edp;
} else { } else {
@ -752,7 +760,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
} }
} }
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
return kbl_get_buf_trans_dp(dev_priv, n_entries); return kbl_get_buf_trans_dp(dev_priv, n_entries);
else else
return skl_get_buf_trans_dp(dev_priv, n_entries); return skl_get_buf_trans_dp(dev_priv, n_entries);
@ -761,8 +771,10 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
static const struct ddi_buf_trans * static const struct ddi_buf_trans *
skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
{ {
if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || if (IS_SKL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv)) { IS_KBL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv) ||
IS_CML_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
return skl_y_ddi_translations_hdmi; return skl_y_ddi_translations_hdmi;
} else { } else {
@ -784,7 +796,9 @@ static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
enum port port, int *n_entries) enum port port, int *n_entries)
{ {
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
const struct ddi_buf_trans *ddi_translations = const struct ddi_buf_trans *ddi_translations =
kbl_get_buf_trans_dp(dev_priv, n_entries); kbl_get_buf_trans_dp(dev_priv, n_entries);
*n_entries = skl_buf_trans_num_entries(port, *n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries);

7
drivers/gpu/drm/i915/display/intel_hdcp.c
View file

@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false; return false;
return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || return (INTEL_GEN(dev_priv) >= 10 ||
IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)); IS_GEMINILAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv));
} }
void intel_hdcp_component_init(struct drm_i915_private *dev_priv) void intel_hdcp_component_init(struct drm_i915_private *dev_priv)

18
drivers/gpu/drm/i915/gt/intel_workarounds.c
View file

@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
HDC_FORCE_NON_COHERENT); HDC_FORCE_NON_COHERENT);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) if (IS_SKYLAKE(i915) ||
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS); GEN8_SAMPLER_POWER_BYPASS_DIS);
@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
icl_ctx_workarounds_init(engine, wal); icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915)) else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal); cnl_ctx_workarounds_init(engine, wal);
else if (IS_COFFEELAKE(i915)) else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
cfl_ctx_workarounds_init(engine, wal); cfl_ctx_workarounds_init(engine, wal);
else if (IS_GEMINILAKE(i915)) else if (IS_GEMINILAKE(i915))
glk_ctx_workarounds_init(engine, wal); glk_ctx_workarounds_init(engine, wal);
@ -706,7 +709,7 @@ static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{ {
/* WaDisableKillLogic:bxt,skl,kbl */ /* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(i915)) if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
wa_write_or(wal, wa_write_or(wal,
GAM_ECOCHK, GAM_ECOCHK,
ECOCHK_DIS_TLB); ECOCHK_DIS_TLB);
@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
icl_gt_workarounds_init(i915, wal); icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915)) else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal); cnl_gt_workarounds_init(i915, wal);
else if (IS_COFFEELAKE(i915)) else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
cfl_gt_workarounds_init(i915, wal); cfl_gt_workarounds_init(i915, wal);
else if (IS_GEMINILAKE(i915)) else if (IS_GEMINILAKE(i915))
glk_gt_workarounds_init(i915, wal); glk_gt_workarounds_init(i915, wal);
@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
icl_whitelist_build(engine); icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915)) else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine); cnl_whitelist_build(engine);
else if (IS_COFFEELAKE(i915)) else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
cfl_whitelist_build(engine); cfl_whitelist_build(engine);
else if (IS_GEMINILAKE(i915)) else if (IS_GEMINILAKE(i915))
glk_whitelist_build(engine); glk_whitelist_build(engine);
@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_FFSC_PERCTX_PREEMPT_CTRL); GEN9_FFSC_PERCTX_PREEMPT_CTRL);
} }
if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { if (IS_SKYLAKE(i915) ||
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915)) {
/* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
wa_write_or(wal, wa_write_or(wal,
GEN8_GARBCNTL, GEN8_GARBCNTL,

2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
View file

@ -55,7 +55,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \ fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \
fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \
fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \
fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ fw_def(COMETLAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \
fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \
fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \
fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \

30
drivers/gpu/drm/i915/gvt/display.c
View file

@ -199,8 +199,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
SDE_PORTC_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT |
SDE_PORTD_HOTPLUG_CPT); SDE_PORTD_HOTPLUG_CPT);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || if (IS_SKYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv)) { IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
SDE_PORTE_HOTPLUG_SPT); SDE_PORTE_HOTPLUG_SPT);
vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
@ -275,8 +277,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
} }
if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || if ((IS_SKYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv)) && IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) &&
intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
} }
@ -459,8 +463,10 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
struct drm_i915_private *i915 = vgpu->gvt->gt->i915; struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
/* TODO: add more platforms support */ /* TODO: add more platforms support */
if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || if (IS_SKYLAKE(i915) ||
IS_COFFEELAKE(i915)) { IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915)) {
if (connected) { if (connected) {
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
SFUSE_STRAP_DDID_DETECTED; SFUSE_STRAP_DDID_DETECTED;
@ -488,8 +494,10 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
{ {
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || if (IS_SKYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv)) IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
clean_virtual_dp_monitor(vgpu, PORT_D); clean_virtual_dp_monitor(vgpu, PORT_D);
else else
clean_virtual_dp_monitor(vgpu, PORT_B); clean_virtual_dp_monitor(vgpu, PORT_B);
@ -512,8 +520,10 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
intel_vgpu_init_i2c_edid(vgpu); intel_vgpu_init_i2c_edid(vgpu);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || if (IS_SKYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv)) IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
resolution); resolution);
else else

2
drivers/gpu/drm/i915/gvt/edid.c
View file

@ -149,7 +149,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
if (IS_BROXTON(i915)) if (IS_BROXTON(i915))
port = bxt_get_port_from_gmbus0(pin_select); port = bxt_get_port_from_gmbus0(pin_select);
else if (IS_COFFEELAKE(i915)) else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
port = cnp_get_port_from_gmbus0(pin_select); port = cnp_get_port_from_gmbus0(pin_select);
else else
port = get_port_from_gmbus0(pin_select); port = get_port_from_gmbus0(pin_select);

17
drivers/gpu/drm/i915/gvt/handlers.c
View file

@ -59,7 +59,7 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
return D_KBL; return D_KBL;
else if (IS_BROXTON(i915)) else if (IS_BROXTON(i915))
return D_BXT; return D_BXT;
else if (IS_COFFEELAKE(i915)) else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
return D_CFL; return D_CFL;
return 0; return 0;
@ -1435,7 +1435,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
case GEN9_PCODE_READ_MEM_LATENCY: case GEN9_PCODE_READ_MEM_LATENCY:
if (IS_SKYLAKE(vgpu->gvt->gt->i915) || if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
IS_KABYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) ||
IS_COFFEELAKE(vgpu->gvt->gt->i915)) { IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
IS_COMETLAKE(vgpu->gvt->gt->i915)) {
/** /**
* "Read memory latency" command on gen9. * "Read memory latency" command on gen9.
* Below memory latency values are read * Below memory latency values are read
@ -1460,7 +1461,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
case SKL_PCODE_CDCLK_CONTROL: case SKL_PCODE_CDCLK_CONTROL:
if (IS_SKYLAKE(vgpu->gvt->gt->i915) || if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
IS_KABYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) ||
IS_COFFEELAKE(vgpu->gvt->gt->i915)) IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
IS_COMETLAKE(vgpu->gvt->gt->i915))
*data0 = SKL_CDCLK_READY_FOR_CHANGE; *data0 = SKL_CDCLK_READY_FOR_CHANGE;
break; break;
case GEN6_PCODE_READ_RC6VIDS: case GEN6_PCODE_READ_RC6VIDS:
@ -1722,7 +1724,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int ret; int ret;
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
IS_COMETLAKE(vgpu->gvt->gt->i915))
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
write_vreg(vgpu, offset, p_data, bytes); write_vreg(vgpu, offset, p_data, bytes);
@ -1731,7 +1734,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
return 0; return 0;
} }
if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
data & _MASKED_BIT_ENABLE(2)) { data & _MASKED_BIT_ENABLE(2)) {
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
return 0; return 0;
@ -3393,7 +3397,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
goto err; goto err;
} else if (IS_SKYLAKE(i915) || } else if (IS_SKYLAKE(i915) ||
IS_KABYLAKE(i915) || IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915)) { IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915)) {
ret = init_bdw_mmio_info(gvt); ret = init_bdw_mmio_info(gvt);
if (ret) if (ret)
goto err; goto err;

9
drivers/gpu/drm/i915/i915_drv.h
View file

@ -1411,6 +1411,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
@ -1459,6 +1460,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
INTEL_INFO(dev_priv)->gt == 2) INTEL_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3) INTEL_INFO(dev_priv)->gt == 3)
#define IS_CML_ULT(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_CML_ULX(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_CNL_WITH_PORT_F(dev_priv) \ #define IS_CNL_WITH_PORT_F(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
#define IS_ICL_WITH_PORT_F(dev_priv) \ #define IS_ICL_WITH_PORT_F(dev_priv) \

22
drivers/gpu/drm/i915/i915_pci.c
View file

@ -766,6 +766,20 @@ static const struct intel_device_info cfl_gt3_info = {
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
}; };
#define CML_PLATFORM \
GEN9_FEATURES, \
PLATFORM(INTEL_COMETLAKE)
static const struct intel_device_info cml_gt1_info = {
CML_PLATFORM,
.gt = 1,
};
static const struct intel_device_info cml_gt2_info = {
CML_PLATFORM,
.gt = 2,
};
#define GEN10_FEATURES \ #define GEN10_FEATURES \
GEN9_FEATURES, \ GEN9_FEATURES, \
GEN(10), \ GEN(10), \
@ -942,10 +956,10 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
INTEL_CML_GT1_IDS(&cfl_gt1_info), INTEL_CML_GT1_IDS(&cml_gt1_info),
INTEL_CML_GT2_IDS(&cfl_gt2_info), INTEL_CML_GT2_IDS(&cml_gt2_info),
INTEL_CML_U_GT1_IDS(&cfl_gt1_info), INTEL_CML_U_GT1_IDS(&cml_gt1_info),
INTEL_CML_U_GT2_IDS(&cfl_gt2_info), INTEL_CML_U_GT2_IDS(&cml_gt2_info),
INTEL_CNL_IDS(&cnl_info), INTEL_CNL_IDS(&cnl_info),
INTEL_ICL_11_IDS(&icl_info), INTEL_ICL_11_IDS(&icl_info),
INTEL_EHL_IDS(&ehl_info), INTEL_EHL_IDS(&ehl_info),

1
drivers/gpu/drm/i915/intel_device_info.c
View file

@ -57,6 +57,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(KABYLAKE), PLATFORM_NAME(KABYLAKE),
PLATFORM_NAME(GEMINILAKE), PLATFORM_NAME(GEMINILAKE),
PLATFORM_NAME(COFFEELAKE), PLATFORM_NAME(COFFEELAKE),
PLATFORM_NAME(COMETLAKE),
PLATFORM_NAME(CANNONLAKE), PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE), PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE), PLATFORM_NAME(ELKHARTLAKE),

1
drivers/gpu/drm/i915/intel_device_info.h
View file

@ -73,6 +73,7 @@ enum intel_platform {
INTEL_KABYLAKE, INTEL_KABYLAKE,
INTEL_GEMINILAKE, INTEL_GEMINILAKE,
INTEL_COFFEELAKE, INTEL_COFFEELAKE,
INTEL_COMETLAKE,
/* gen10 */ /* gen10 */
INTEL_CANNONLAKE, INTEL_CANNONLAKE,
/* gen11 */ /* gen11 */

2
drivers/gpu/drm/i915/intel_gvt.c
View file

@ -52,6 +52,8 @@ static bool is_supported_device(struct drm_i915_private *dev_priv)
return true; return true;
if (IS_COFFEELAKE(dev_priv)) if (IS_COFFEELAKE(dev_priv))
return true; return true;
if (IS_COMETLAKE(dev_priv))
return true;
return false; return false;
} }

36
drivers/gpu/drm/i915/intel_pch.c
View file

@ -64,37 +64,49 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n");
drm_WARN_ON(&dev_priv->drm, drm_WARN_ON(&dev_priv->drm,
!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && !IS_SKYLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv)); !IS_KABYLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv));
return PCH_SPT; return PCH_SPT;
case INTEL_PCH_KBP_DEVICE_ID_TYPE: case INTEL_PCH_KBP_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n");
drm_WARN_ON(&dev_priv->drm, drm_WARN_ON(&dev_priv->drm,
!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && !IS_SKYLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv)); !IS_KABYLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv));
/* KBP is SPT compatible */ /* KBP is SPT compatible */
return PCH_SPT; return PCH_SPT;
case INTEL_PCH_CNP_DEVICE_ID_TYPE: case INTEL_PCH_CNP_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && drm_WARN_ON(&dev_priv->drm,
!IS_COFFEELAKE(dev_priv)); !IS_CANNONLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv));
return PCH_CNP; return PCH_CNP;
case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, drm_dbg_kms(&dev_priv->drm,
"Found Cannon Lake LP PCH (CNP-LP)\n"); "Found Cannon Lake LP PCH (CNP-LP)\n");
drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && drm_WARN_ON(&dev_priv->drm,
!IS_COFFEELAKE(dev_priv)); !IS_CANNONLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv));
return PCH_CNP; return PCH_CNP;
case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP_DEVICE_ID_TYPE:
case INTEL_PCH_CMP2_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n");
drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && drm_WARN_ON(&dev_priv->drm,
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv) &&
!IS_ROCKETLAKE(dev_priv)); !IS_ROCKETLAKE(dev_priv));
/* CometPoint is CNP Compatible */ /* CometPoint is CNP Compatible */
return PCH_CNP; return PCH_CNP;
case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); drm_WARN_ON(&dev_priv->drm,
!IS_COFFEELAKE(dev_priv) &&
!IS_COMETLAKE(dev_priv));
/* Comet Lake V PCH is based on KBP, which is SPT compatible */ /* Comet Lake V PCH is based on KBP, which is SPT compatible */
return PCH_SPT; return PCH_SPT;
case INTEL_PCH_ICP_DEVICE_ID_TYPE: case INTEL_PCH_ICP_DEVICE_ID_TYPE:
@ -149,7 +161,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
id = INTEL_PCH_MCC_DEVICE_ID_TYPE; id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
else if (IS_ICELAKE(dev_priv)) else if (IS_ICELAKE(dev_priv))
id = INTEL_PCH_ICP_DEVICE_ID_TYPE; id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) else if (IS_CANNONLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
id = INTEL_PCH_CNP_DEVICE_ID_TYPE; id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
id = INTEL_PCH_SPT_DEVICE_ID_TYPE; id = INTEL_PCH_SPT_DEVICE_ID_TYPE;

10
drivers/gpu/drm/i915/intel_pm.c
View file

@ -5256,7 +5256,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
* WaIncreaseLatencyIPCEnabled: kbl,cfl * WaIncreaseLatencyIPCEnabled: kbl,cfl
* Display WA #1141: kbl,cfl * Display WA #1141: kbl,cfl
*/ */
if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && if ((IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) &&
dev_priv->ipc_enabled) dev_priv->ipc_enabled)
latency += 4; latency += 4;
@ -6822,7 +6824,9 @@ static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
return false; return false;
/* Display WA #1141: SKL:all KBL:all CFL */ /* Display WA #1141: SKL:all KBL:all CFL */
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
return dev_priv->dram_info.symmetric_memory; return dev_priv->dram_info.symmetric_memory;
return true; return true;
@ -7703,7 +7707,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = icl_init_clock_gating; dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv)) else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating; dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv)) else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating; dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv)) else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating; dev_priv->display.init_clock_gating = skl_init_clock_gating;