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drm/mediatek: Move cmdq_reg info from struct mtk_ddp_comp to sub driver private data

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Some ddp component exist in both display path and other path, so data
belonged to sub driver should be moved into sub driver private data so it
could be used for multiple path. cmdq_reg info is one of sub driver data,
so move it.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
CK Hu 2020-10-08 13:41:10 +08:00 • committed by Chun-Kuang Hu
parent f22a565d10
commit 616443ca57
5 changed files with 84 additions and 64 deletions
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10
drivers/gpu/drm/mediatek/mtk_disp_color.c
View file

@ -40,6 +40,7 @@ struct mtk_disp_color {
struct drm_crtc *crtc; struct drm_crtc *crtc;
struct clk *clk; struct clk *clk;
void __iomem *regs; void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
const struct mtk_disp_color_data *data; const struct mtk_disp_color_data *data;
}; };
@ -68,8 +69,8 @@ static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_disp_color *color = comp_to_color(comp); struct mtk_disp_color *color = comp_to_color(comp);
mtk_ddp_write(cmdq_pkt, w, comp, color->regs, DISP_COLOR_WIDTH(color)); mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color));
mtk_ddp_write(cmdq_pkt, h, comp, color->regs, DISP_COLOR_HEIGHT(color)); mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color));
} }
static void mtk_color_start(struct mtk_ddp_comp *comp) static void mtk_color_start(struct mtk_ddp_comp *comp)
@ -143,6 +144,11 @@ static int mtk_disp_color_probe(struct platform_device *pdev)
dev_err(dev, "failed to ioremap color\n"); dev_err(dev, "failed to ioremap color\n");
return PTR_ERR(priv->regs); return PTR_ERR(priv->regs);
} }
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
#endif
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR); comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR);
if (comp_id < 0) { if (comp_id < 0) {

34
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
View file

@ -74,6 +74,7 @@ struct mtk_disp_ovl {
struct drm_crtc *crtc; struct drm_crtc *crtc;
struct clk *clk; struct clk *clk;
void __iomem *regs; void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
const struct mtk_disp_ovl_data *data; const struct mtk_disp_ovl_data *data;
}; };
@ -151,12 +152,12 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev);
if (w != 0 && h != 0) if (w != 0 && h != 0)
mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_ROI_SIZE); DISP_REG_OVL_ROI_SIZE);
mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_ROI_BGCLR); mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
mtk_ddp_write(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
} }
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
@ -208,7 +209,7 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
unsigned int gmc_value; unsigned int gmc_value;
struct mtk_disp_ovl *ovl = comp_to_ovl(comp); struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_RDMA_CTRL(idx)); DISP_REG_OVL_RDMA_CTRL(idx));
gmc_thrshd_l = GMC_THRESHOLD_LOW >> gmc_thrshd_l = GMC_THRESHOLD_LOW >>
(GMC_THRESHOLD_BITS - ovl->data->gmc_bits); (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
@ -220,8 +221,8 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
gmc_thrshd_h << 16 | gmc_thrshd_h << 24; gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
mtk_ddp_write(cmdq_pkt, gmc_value, mtk_ddp_write(cmdq_pkt, gmc_value,
comp, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp, ovl->regs, mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_SRC_CON, BIT(idx)); DISP_REG_OVL_SRC_CON, BIT(idx));
} }
@ -230,9 +231,9 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
{ {
struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev);
mtk_ddp_write_mask(cmdq_pkt, 0, comp, ovl->regs, mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_SRC_CON, BIT(idx)); DISP_REG_OVL_SRC_CON, BIT(idx));
mtk_ddp_write(cmdq_pkt, 0, comp, ovl->regs, mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_RDMA_CTRL(idx)); DISP_REG_OVL_RDMA_CTRL(idx));
} }
@ -304,15 +305,15 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
addr += pending->pitch - 1; addr += pending->pitch - 1;
} }
mtk_ddp_write_relaxed(cmdq_pkt, con, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_CON(idx)); DISP_REG_OVL_CON(idx));
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_PITCH(idx)); DISP_REG_OVL_PITCH(idx));
mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_SRC_SIZE(idx)); DISP_REG_OVL_SRC_SIZE(idx));
mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_OFFSET(idx)); DISP_REG_OVL_OFFSET(idx));
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, ovl->regs, mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_ADDR(ovl, idx)); DISP_REG_OVL_ADDR(ovl, idx));
mtk_ovl_layer_on(comp, idx, cmdq_pkt); mtk_ovl_layer_on(comp, idx, cmdq_pkt);
@ -414,6 +415,11 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
dev_err(dev, "failed to ioremap ovl\n"); dev_err(dev, "failed to ioremap ovl\n");
return PTR_ERR(priv->regs); return PTR_ERR(priv->regs);
} }
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
#endif
priv->data = of_device_get_match_data(dev); priv->data = of_device_get_match_data(dev);

30
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
View file

@ -65,6 +65,7 @@ struct mtk_disp_rdma {
struct drm_crtc *crtc; struct drm_crtc *crtc;
struct clk *clk; struct clk *clk;
void __iomem *regs; void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
const struct mtk_disp_rdma_data *data; const struct mtk_disp_rdma_data *data;
}; };
@ -150,9 +151,9 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int reg; unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp); struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
mtk_ddp_write_mask(cmdq_pkt, width, comp, rdma->regs, mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
DISP_REG_RDMA_SIZE_CON_0, 0xfff); DISP_REG_RDMA_SIZE_CON_0, 0xfff);
mtk_ddp_write_mask(cmdq_pkt, height, comp, rdma->regs, mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
DISP_REG_RDMA_SIZE_CON_1, 0xfffff); DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
/* /*
@ -165,7 +166,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
reg = RDMA_FIFO_UNDERFLOW_EN | reg = RDMA_FIFO_UNDERFLOW_EN |
RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
mtk_ddp_write(cmdq_pkt, reg, comp, rdma->regs, DISP_REG_RDMA_FIFO_CON); mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
} }
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
@ -222,25 +223,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
unsigned int con; unsigned int con;
con = rdma_fmt_convert(rdma, fmt); con = rdma_fmt_convert(rdma, fmt);
mtk_ddp_write_relaxed(cmdq_pkt, con, comp, rdma->regs, DISP_RDMA_MEM_CON); mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, rdma->regs, mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
DISP_REG_RDMA_SIZE_CON_0, DISP_REG_RDMA_SIZE_CON_0,
RDMA_MATRIX_ENABLE); RDMA_MATRIX_ENABLE);
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
RDMA_MATRIX_INT_MTX_SEL); RDMA_MATRIX_INT_MTX_SEL);
} else { } else {
mtk_ddp_write_mask(cmdq_pkt, 0, comp, rdma->regs, mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
DISP_REG_RDMA_SIZE_CON_0, DISP_REG_RDMA_SIZE_CON_0,
RDMA_MATRIX_ENABLE); RDMA_MATRIX_ENABLE);
} }
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, rdma->regs, DISP_RDMA_MEM_START_ADDR); mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, rdma->regs, DISP_RDMA_MEM_SRC_PITCH); DISP_RDMA_MEM_START_ADDR);
mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, rdma->regs, mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
DISP_RDMA_MEM_SRC_PITCH);
mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
DISP_RDMA_MEM_GMC_SETTING_0); DISP_RDMA_MEM_GMC_SETTING_0);
mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, rdma->regs, mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
} }
@ -318,6 +321,11 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
dev_err(dev, "failed to ioremap rdma\n"); dev_err(dev, "failed to ioremap rdma\n");
return PTR_ERR(priv->regs); return PTR_ERR(priv->regs);
} }
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
#endif
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA);
if (comp_id < 0) { if (comp_id < 0) {

67
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
View file

@ -88,42 +88,43 @@
struct mtk_ddp_comp_dev { struct mtk_ddp_comp_dev {
struct clk *clk; struct clk *clk;
void __iomem *regs; void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
}; };
void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset) unsigned int offset)
{ {
#if IS_REACHABLE(CONFIG_MTK_CMDQ) #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (cmdq_pkt) if (cmdq_pkt)
cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
comp->cmdq_reg.offset + offset, value); cmdq_reg->offset + offset, value);
else else
#endif #endif
writel(value, regs + offset); writel(value, regs + offset);
} }
void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset) unsigned int offset)
{ {
#if IS_REACHABLE(CONFIG_MTK_CMDQ) #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (cmdq_pkt) if (cmdq_pkt)
cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
comp->cmdq_reg.offset + offset, value); cmdq_reg->offset + offset, value);
else else
#endif #endif
writel_relaxed(value, regs + offset); writel_relaxed(value, regs + offset);
} }
void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset, unsigned int mask) unsigned int offset, unsigned int mask)
{ {
#if IS_REACHABLE(CONFIG_MTK_CMDQ) #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (cmdq_pkt) { if (cmdq_pkt) {
cmdq_pkt_write_mask(cmdq_pkt, comp->cmdq_reg.subsys, cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
comp->cmdq_reg.offset + offset, value, mask); cmdq_reg->offset + offset, value, mask);
} else { } else {
#endif #endif
u32 tmp = readl(regs + offset); u32 tmp = readl(regs + offset);
@ -159,20 +160,20 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
return; return;
if (bpc >= MTK_MIN_BPC) { if (bpc >= MTK_MIN_BPC) {
mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5);
mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7);
mtk_ddp_write(cmdq_pkt, mtk_ddp_write(cmdq_pkt,
DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
DITHER_NEW_BIT_MODE, DITHER_NEW_BIT_MODE,
comp, priv->regs, DISP_DITHER_15); &priv->cmdq_reg, priv->regs, DISP_DITHER_15);
mtk_ddp_write(cmdq_pkt, mtk_ddp_write(cmdq_pkt,
DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
comp, priv->regs, DISP_DITHER_16); &priv->cmdq_reg, priv->regs, DISP_DITHER_16);
mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, priv->regs, CFG); mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG);
} }
} }
@ -182,8 +183,8 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev);
mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, priv->regs, DISP_OD_SIZE); mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, priv->regs, DISP_OD_CFG); mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
} }
@ -207,7 +208,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev);
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_AAL_SIZE); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
} }
static void mtk_aal_start(struct mtk_ddp_comp *comp) static void mtk_aal_start(struct mtk_ddp_comp *comp)
@ -230,8 +231,8 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev);
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE);
mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, priv->regs, DISP_CCORR_CFG); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG);
} }
static void mtk_ccorr_start(struct mtk_ddp_comp *comp) static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@ -289,15 +290,15 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
comp, priv->regs, DISP_CCORR_COEF_0); &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0);
mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
comp, priv->regs, DISP_CCORR_COEF_1); &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1);
mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
comp, priv->regs, DISP_CCORR_COEF_2); &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2);
mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
comp, priv->regs, DISP_CCORR_COEF_3); &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3);
mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
comp, priv->regs, DISP_CCORR_COEF_4); &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4);
} }
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
@ -306,8 +307,8 @@ static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev);
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_DITHER_SIZE); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, priv->regs, DISP_DITHER_CFG); mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
} }
static void mtk_dither_start(struct mtk_ddp_comp *comp) static void mtk_dither_start(struct mtk_ddp_comp *comp)
@ -330,7 +331,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
{ {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev);
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_GAMMA_SIZE); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE);
mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
} }
@ -586,12 +587,6 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
} }
comp->dev = &comp_pdev->dev; comp->dev = &comp_pdev->dev;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_reg, 0);
if (ret)
dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
#endif
/* Only DMA capable components need the LARB property */ /* Only DMA capable components need the LARB property */
if (type == MTK_DISP_OVL || if (type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L || type == MTK_DISP_OVL_2L ||
@ -617,6 +612,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
if (IS_ERR(priv->clk)) if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk); return PTR_ERR(priv->clk);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
if (ret)
dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
#endif
platform_set_drvdata(comp_pdev, priv); platform_set_drvdata(comp_pdev, priv);
return 0; return 0;

7
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
View file

@ -71,7 +71,6 @@ struct mtk_ddp_comp {
struct device *larb_dev; struct device *larb_dev;
enum mtk_ddp_comp_id id; enum mtk_ddp_comp_id id;
const struct mtk_ddp_comp_funcs *funcs; const struct mtk_ddp_comp_funcs *funcs;
struct cmdq_client_reg cmdq_reg;
}; };
static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp) static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp)
@ -195,12 +194,12 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
unsigned int CFG, struct cmdq_pkt *cmdq_pkt); unsigned int CFG, struct cmdq_pkt *cmdq_pkt);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset); unsigned int offset);
void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset); unsigned int offset);
void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, void __iomem *regs, struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
unsigned int offset, unsigned int mask); unsigned int offset, unsigned int mask);
#endif /* MTK_DRM_DDP_COMP_H */ #endif /* MTK_DRM_DDP_COMP_H */