drm/i915/display: move hti under display sub-struct
Move display hti/hdport related members under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221109144209.3624739-2-jani.nikula@intel.com
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6274991254
3 changed files with 15 additions and 13 deletions
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@ -370,6 +370,16 @@ struct intel_display {
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struct mutex comp_mutex;
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} hdcp;
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struct {
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/*
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* HTI (aka HDPORT) state read during initial hw readout. Most
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* platforms don't have HTI, so this will just stay 0. Those
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* that do will use this later to figure out which PLLs and PHYs
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* are unavailable for driver usage.
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*/
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u32 state;
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} hti;
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struct {
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struct i915_power_domains domains;
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@ -16,23 +16,23 @@ void intel_hti_init(struct drm_i915_private *i915)
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* any display resources before we create our display outputs.
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*/
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if (INTEL_INFO(i915)->display.has_hti)
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i915->hti_state = intel_de_read(i915, HDPORT_STATE);
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i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
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}
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bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
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{
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return i915->hti_state & HDPORT_ENABLED &&
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i915->hti_state & HDPORT_DDI_USED(phy);
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return i915->display.hti.state & HDPORT_ENABLED &&
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i915->display.hti.state & HDPORT_DDI_USED(phy);
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}
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u32 intel_hti_dpll_mask(struct drm_i915_private *i915)
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{
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if (!(i915->hti_state & HDPORT_ENABLED))
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if (!(i915->display.hti.state & HDPORT_ENABLED))
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return 0;
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/*
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* Note: This is subtle. The values must coincide with what's defined
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* for the platform.
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*/
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return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
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return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state);
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}
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@ -300,14 +300,6 @@ struct drm_i915_private {
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struct intel_l3_parity l3_parity;
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/*
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* HTI (aka HDPORT) state read during initial hw readout. Most
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* platforms don't have HTI, so this will just stay 0. Those that do
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* will use this later to figure out which PLLs and PHYs are unavailable
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* for driver usage.
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*/
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u32 hti_state;
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/*
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* edram size in MB.
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* Cannot be determined by PCIID. You must always read a register.
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