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hwmon: (k8temp) Remove superfluous CPU family check

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The family check in k8temp is not required because the driver is
already bound to a northbridge device only used with K8 CPUs.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Andreas Herrmann 2010-10-28 20:31:42 +02:00 • committed by Jean Delvare
parent 81280572ca
commit 628b4504cf
1 changed files with 23 additions and 30 deletions
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53
drivers/hwmon/k8temp.c
View file

@ -191,38 +191,31 @@ static int __devinit k8temp_probe(struct pci_dev *pdev,
model = boot_cpu_data.x86_model; model = boot_cpu_data.x86_model;
stepping = boot_cpu_data.x86_mask; stepping = boot_cpu_data.x86_mask;
switch (boot_cpu_data.x86) { /* feature available since SH-C0, exclude older revisions */
case 0xf: if (((model == 4) && (stepping == 0)) ||
/* feature available since SH-C0, exclude older revisions */ ((model == 5) && (stepping <= 1))) {
if (((model == 4) && (stepping == 0)) || err = -ENODEV;
((model == 5) && (stepping <= 1))) { goto exit_free;
err = -ENODEV;
goto exit_free;
}
/*
* AMD NPT family 0fh, i.e. RevF and RevG:
* meaning of SEL_CORE bit is inverted
*/
if (model >= 0x40) {
data->swap_core_select = 1;
dev_warn(&pdev->dev, "Temperature readouts might be "
"wrong - check erratum #141\n");
}
if (is_rev_g_desktop(model)) {
/*
* RevG desktop CPUs (i.e. no socket S1G1 or
* ASB1 parts) need additional offset,
* otherwise reported temperature is below
* ambient temperature
*/
data->temp_offset = 21000;
}
break;
} }
/*
* AMD NPT family 0fh, i.e. RevF and RevG:
* meaning of SEL_CORE bit is inverted
*/
if (model >= 0x40) {
data->swap_core_select = 1;
dev_warn(&pdev->dev, "Temperature readouts might be wrong - "
"check erratum #141\n");
}
/*
* RevG desktop CPUs (i.e. no socket S1G1 or ASB1 parts) need
* additional offset, otherwise reported temperature is below
* ambient temperature
*/
if (is_rev_g_desktop(model))
data->temp_offset = 21000;
pci_read_config_byte(pdev, REG_TEMP, &scfg); pci_read_config_byte(pdev, REG_TEMP, &scfg);
scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */ scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */
pci_write_config_byte(pdev, REG_TEMP, scfg); pci_write_config_byte(pdev, REG_TEMP, scfg);