A bunch of changes including mali gpu nodes for rk3288 boards
following (and including) the new Mali Midgard binding; a lot of improvements for the rk3228/rk3229 socs (tsadc, operating points, usb, clock-rates, pinctrl, watchdog); finalizing the rk1108->rv1108 rename and adc buttons for the rk3288 firefly boards. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlk5x+gQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgVOmB/sHN5YBQCwdlermcO75CiLktacneQ6qcom2 GCBHfKwXxmey7puB8cKfQ1IgvvsKmXU1+QbUDjxD13p7b139WVRM3VEokOiSR7cl XjGFFy9u6ECfPRpJfPBN/8oENcZ1N94S3gfhCwgcF6JDkumMI4DWVTLD4lZLeIcR LTfZMddSevITXMzrWh0+Q9/TgnJbD58x4lSxs5m85h/8JDSfqdsijs/j2HJrBHPv 01NwQBm8w6rmTNL3UGfqDeUZTnmaczXRf2sgEr5ORLln2Qn++FpUaJiRPUdtYRs7 NEWLppFQeykoxgTQnttkt8oOyaKfNS3PsvwgA7R35w5HnbEtXcDK =b2HZ -----END PGP SIGNATURE----- Merge tag 'v4.13-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt A bunch of changes including mali gpu nodes for rk3288 boards following (and including) the new Mali Midgard binding; a lot of improvements for the rk3228/rk3229 socs (tsadc, operating points, usb, clock-rates, pinctrl, watchdog); finalizing the rk1108->rv1108 rename and adc buttons for the rk3288 firefly boards. * tag 'v4.13-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: enable usb for rk3229 evb board ARM: dts: rockchip: add usb nodes on rk322x ARM: dts: rockchip: add adc button for Firefly ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly ARM: dts: rockchip: enable ARM Mali GPU on rk3288-rock2-som ARM: dts: rockchip: add ARM Mali GPU node for rk3288 dt-bindings: gpu: add bindings for the ARM Mali Midgard GPU ARM: dts: rockchip: set a sane frequence for tsadc on rk322x ARM: dts: rockchip: add operating-points-v2 for cpu on rk322x ARM: dts: rockchip: set default rates for core clocks on rk322x ARM: dts: rockchip: add second uart2 pinctrl on rk322x ARM: dts: rockchip: correct rk322x uart2 pinctrl ARM: dts: rockchip: add watchdog device node on rk322x clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399 ARM: dts: rockchip: fix rk322x i2s1 pinctrl error ARM: dts: rockchip: rename RK1108-evb to RV1108-evb ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 ARM: dts: rockchip: Setup usb vbus-supply on rk3288-rock2 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
63a677bca2
15 changed files with 517 additions and 31 deletions
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@ -138,9 +138,9 @@ Rockchip platforms device tree bindings
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Required root node properties:
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- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
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- Rockchip RK1108 Evaluation board
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- Rockchip RV1108 Evaluation board
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Required root node properties:
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- compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
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- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
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- Rockchip RK3368 evb:
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Required root node properties:
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86
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
Normal file
86
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
Normal file
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@ -0,0 +1,86 @@
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ARM Mali Midgard GPU
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====================
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Required properties:
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- compatible :
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* Must contain one of the following:
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+ "arm,mali-t604"
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+ "arm,mali-t624"
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+ "arm,mali-t628"
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+ "arm,mali-t720"
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+ "arm,mali-t760"
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+ "arm,mali-t820"
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+ "arm,mali-t830"
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+ "arm,mali-t860"
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+ "arm,mali-t880"
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* which must be preceded by one of the following vendor specifics:
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+ "amlogic,meson-gxm-mali"
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+ "rockchip,rk3288-mali"
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- reg : Physical base address of the device and length of the register area.
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- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
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- interrupt-names : Contains the names of IRQ resources in the order they were
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provided in the interrupts property. Must contain: "job", "mmu", "gpu".
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Optional properties:
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- clocks : Phandle to clock for the Mali Midgard device.
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- mali-supply : Phandle to regulator for the Mali device. Refer to
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Documentation/devicetree/bindings/regulator/regulator.txt for details.
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- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt
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for details.
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Example for a Mali-T760:
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gpu@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
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reg = <0xffa30000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "job", "mmu", "gpu";
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clocks = <&cru ACLK_GPU>;
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mali-supply = <&vdd_gpu>;
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operating-points-v2 = <&gpu_opp_table>;
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power-domains = <&power RK3288_PD_GPU>;
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};
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gpu_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp@533000000 {
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opp-hz = /bits/ 64 <533000000>;
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opp-microvolt = <1250000>;
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};
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opp@450000000 {
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opp-hz = /bits/ 64 <450000000>;
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opp-microvolt = <1150000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1125000>;
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};
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opp@350000000 {
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opp-hz = /bits/ 64 <350000000>;
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opp-microvolt = <1075000>;
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};
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opp@266000000 {
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opp-hz = /bits/ 64 <266000000>;
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opp-microvolt = <1025000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <925000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <912500>;
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};
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};
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@ -719,7 +719,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
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r8a7794-silk.dtb \
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sh73a0-kzm9g.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk1108-evb.dtb \
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rv1108-evb.dtb \
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rk3036-evb.dtb \
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rk3036-kylin.dtb \
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rk3066a-bqcurie2.dtb \
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@ -58,6 +58,17 @@
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#clock-cells = <0>;
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};
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vcc_host: vcc-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&host_vbus_drv>;
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regulator-name = "vcc_host";
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regulator-always-on;
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regulator-boot-on;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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@ -85,6 +96,69 @@
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status = "okay";
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};
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&pinctrl {
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usb {
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host_vbus_drv: host-vbus-drv {
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rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&uart2 {
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status = "okay";
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};
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&u2phy0 {
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status = "okay";
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u2phy0_otg: otg-port {
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status = "okay";
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};
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u2phy0_host: host-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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};
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&u2phy1 {
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status = "okay";
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u2phy1_otg: otg-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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u2phy1_host: host-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&usb_host1_ohci {
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status = "okay";
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};
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&usb_host2_ehci {
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status = "okay";
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};
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&usb_host2_ohci {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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};
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@ -66,10 +66,7 @@
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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@ -80,6 +77,7 @@
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu2: cpu@f02 {
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@ -87,6 +85,7 @@
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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resets = <&cru SRST_CORE2>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu3: cpu@f03 {
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@ -94,6 +93,35 @@
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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resets = <&cru SRST_CORE3>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <975000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1000000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1175000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1275000>;
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};
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};
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@ -182,8 +210,61 @@
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};
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grf: syscon@11000000 {
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compatible = "syscon";
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compatible = "syscon", "simple-mfd";
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reg = <0x11000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy0: usb2-phy@760 {
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compatible = "rockchip,rk3228-usb2phy";
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reg = <0x0760 0x0c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy0";
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#clock-cells = <0>;
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status = "disabled";
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u2phy0_otg: otg-port {
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id",
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"linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy0_host: host-port {
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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u2phy1: usb2-phy@800 {
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compatible = "rockchip,rk3228-usb2phy";
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reg = <0x0800 0x0c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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status = "disabled";
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u2phy1_otg: otg-port {
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy1_host: host-port {
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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uart0: serial@11010000 {
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@ -280,6 +361,14 @@
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status = "disabled";
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};
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wdt: watchdog@110a0000 {
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compatible = "snps,dw-wdt";
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reg = <0x110a0000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_CPU>;
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status = "disabled";
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};
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pwm0: pwm@110b0000 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0000 0x10>;
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@ -338,8 +427,18 @@
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru ARMCLK>,
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<&cru PLL_CPLL>, <&cru ACLK_PERI>,
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<&cru HCLK_PERI>, <&cru PCLK_PERI>,
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<&cru ACLK_CPU>, <&cru HCLK_CPU>,
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<&cru PCLK_CPU>;
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assigned-clock-rates =
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<594000000>, <816000000>,
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<500000000>, <150000000>,
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<150000000>, <75000000>,
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<150000000>, <150000000>,
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<75000000>;
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};
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thermal-zones {
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@ -388,6 +487,8 @@
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
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clock-names = "tsadc", "apb_pclk";
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assigned-clocks = <&cru SCLK_TSADC>;
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assigned-clock-rates = <32768>;
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resets = <&cru SRST_TSADC>;
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reset-names = "tsadc-apb";
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pinctrl-names = "init", "default", "sleep";
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@ -419,6 +520,89 @@
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status = "disabled";
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||||
};
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||||
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||||
usb_otg: usb@30040000 {
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compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
|
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reg = <0x30040000 0x40000>;
|
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&cru HCLK_OTG>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "otg";
|
||||
g-np-tx-fifo-size = <16>;
|
||||
g-rx-fifo-size = <280>;
|
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g-tx-fifo-size = <256 128 128 64 32 16>;
|
||||
g-use-dma;
|
||||
phys = <&u2phy0_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@30080000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x30080000 0x20000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
phys = <&u2phy0_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ohci: usb@300a0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x300a0000 0x20000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
phys = <&u2phy0_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ehci: usb@300c0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x300c0000 0x20000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
phys = <&u2phy1_otg>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ohci: usb@300e0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x300e0000 0x20000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
phys = <&u2phy1_otg>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host2_ehci: usb@30100000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x30100000 0x20000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
|
||||
phys = <&u2phy1_host>;
|
||||
phy-names = "usb";
|
||||
clock-names = "usbhost", "utmi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host2_ohci: usb@30120000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x30120000 0x20000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
phys = <&u2phy1_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: ethernet@30200000 {
|
||||
compatible = "rockchip,rk3228-gmac";
|
||||
reg = <0x30200000 0x10000>;
|
||||
|
|
@ -621,9 +805,9 @@
|
|||
<0 12 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 13 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 14 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
<1 2 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 4 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 5 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -693,10 +877,15 @@
|
|||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart21_xfer: uart21-xfer {
|
||||
rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<1 9 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_cts: uart2-cts {
|
||||
rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,6 +48,19 @@
|
|||
model = "Firefly-RK3288-reload";
|
||||
compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
|
||||
button-recovery {
|
||||
label = "Recovery";
|
||||
linux,code = <KEY_VENDOR>;
|
||||
press-threshold-microvolt = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -246,6 +259,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,19 @@
|
|||
reg = <0 0x80000000>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
|
||||
button-recovery {
|
||||
label = "Recovery";
|
||||
linux,code = <KEY_VENDOR>;
|
||||
press-threshold-microvolt = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dovdd_1v8: dovdd-1v8-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dovdd_1v8";
|
||||
|
|
@ -219,6 +232,11 @@
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -113,6 +113,11 @@
|
|||
tx_delay = <0x30>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -125,10 +125,6 @@
|
|||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
/* Always on as the rockchip usb phy doesn't have a vbus-supply
|
||||
* property
|
||||
*/
|
||||
regulator-always-on;
|
||||
regulator-name = "vcc_host";
|
||||
};
|
||||
|
||||
|
|
@ -279,6 +275,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy1 {
|
||||
vbus-supply = <&vcc_usb_host>;
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -161,6 +161,11 @@
|
|||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/clock/rk3288-cru.h>
|
||||
#include <dt-bindings/power/rk3288-power.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/power/rk3288-power.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
|
|
@ -1125,6 +1126,48 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpu: mali@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
||||
reg = <0xffa30000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&power RK3288_PD_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_opp_table: gpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
};
|
||||
opp@500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <1200000>;
|
||||
};
|
||||
opp@600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
};
|
||||
|
||||
qos_gpu_r: qos@ffaa0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xffaa0000 0x20>;
|
||||
|
|
|
|||
|
|
@ -40,11 +40,11 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk1108.dtsi"
|
||||
#include "rv1108.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK1108 Evaluation board";
|
||||
compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
|
||||
model = "Rockchip RV1108 Evaluation board";
|
||||
compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "rockchip,rk1108";
|
||||
compatible = "rockchip,rv1108";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
|
|
@ -113,7 +113,7 @@
|
|||
};
|
||||
|
||||
uart2: serial@10210000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10210000 0x100>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -127,7 +127,7 @@
|
|||
};
|
||||
|
||||
uart1: serial@10220000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10220000 0x100>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -141,7 +141,7 @@
|
|||
};
|
||||
|
||||
uart0: serial@10230000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10230000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -155,17 +155,17 @@
|
|||
};
|
||||
|
||||
grf: syscon@10300000 {
|
||||
compatible = "rockchip,rk1108-grf", "syscon";
|
||||
compatible = "rockchip,rv1108-grf", "syscon";
|
||||
reg = <0x10300000 0x1000>;
|
||||
};
|
||||
|
||||
pmugrf: syscon@20060000 {
|
||||
compatible = "rockchip,rk1108-pmugrf", "syscon";
|
||||
compatible = "rockchip,rv1108-pmugrf", "syscon";
|
||||
reg = <0x20060000 0x1000>;
|
||||
};
|
||||
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rk1108-cru";
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
|
|
@ -173,7 +173,7 @@
|
|||
};
|
||||
|
||||
emmc: dwmmc@30110000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
|
|
@ -185,7 +185,7 @@
|
|||
};
|
||||
|
||||
sdio: dwmmc@30120000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
|
|
@ -197,7 +197,7 @@
|
|||
};
|
||||
|
||||
sdmmc: dwmmc@30130000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 100000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
|
|
@ -61,6 +61,17 @@
|
|||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_MAC_PHY 131
|
||||
#define SCLK_MAC_OUT 132
|
||||
#define SCLK_VDEC_CABAC 133
|
||||
#define SCLK_VDEC_CORE 134
|
||||
#define SCLK_RGA 135
|
||||
#define SCLK_HDCP 136
|
||||
#define SCLK_HDMI_CEC 137
|
||||
#define SCLK_CRYPTO 138
|
||||
#define SCLK_TSP 139
|
||||
#define SCLK_HSADC 140
|
||||
#define SCLK_WIFI 141
|
||||
#define SCLK_OTGPHY0 142
|
||||
#define SCLK_OTGPHY1 143
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
|
|
@ -68,15 +79,32 @@
|
|||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_CPU 195
|
||||
#define ACLK_VPU_PRE 196
|
||||
#define ACLK_RKVDEC_PRE 197
|
||||
#define ACLK_RGA_PRE 198
|
||||
#define ACLK_IEP_PRE 199
|
||||
#define ACLK_HDCP_PRE 200
|
||||
#define ACLK_VOP_PRE 201
|
||||
#define ACLK_VPU 202
|
||||
#define ACLK_RKVDEC 203
|
||||
#define ACLK_IEP 204
|
||||
#define ACLK_RGA 205
|
||||
#define ACLK_HDCP 206
|
||||
#define ACLK_PERI 210
|
||||
#define ACLK_VOP 211
|
||||
#define ACLK_GMAC 212
|
||||
#define ACLK_GPU 213
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_VIO_H2P 324
|
||||
#define PCLK_HDCP 325
|
||||
#define PCLK_EFUSE_1024 326
|
||||
#define PCLK_EFUSE_256 327
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
|
|
@ -89,6 +117,7 @@
|
|||
#define PCLK_TSADC 344
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_CPU 354
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
|
|
@ -104,6 +133,24 @@
|
|||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_CPU 460
|
||||
#define HCLK_VPU_PRE 461
|
||||
#define HCLK_RKVDEC_PRE 462
|
||||
#define HCLK_VIO_PRE 463
|
||||
#define HCLK_VPU 464
|
||||
#define HCLK_RKVDEC 465
|
||||
#define HCLK_VIO 466
|
||||
#define HCLK_RGA 467
|
||||
#define HCLK_IEP 468
|
||||
#define HCLK_VIO_H2P 469
|
||||
#define HCLK_HDCP_MMU 470
|
||||
#define HCLK_HOST0 471
|
||||
#define HCLK_HOST1 472
|
||||
#define HCLK_HOST2 473
|
||||
#define HCLK_OTG 474
|
||||
#define HCLK_TSP 475
|
||||
#define HCLK_M_CRYPTO 476
|
||||
#define HCLK_S_CRYPTO 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@
|
|||
#define SCLK_RMII_SRC 166
|
||||
#define SCLK_PCIEPHY_REF100M 167
|
||||
#define SCLK_DDRC 168
|
||||
#define SCLK_TESTCLKOUT1 169
|
||||
#define SCLK_TESTCLKOUT2 170
|
||||
|
||||
#define DCLK_VOP0 180
|
||||
#define DCLK_VOP1 181
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue