dmaengine: tegra-apb: Improve DMA synchronization
Boot CPU0 always handles DMA interrupts and under some rare circumstances it could stuck in uninterruptible state for a significant time (like in a case of KASAN + NFS root). In this case sibling CPU, which waits for DMA transfer completion, will get a DMA transfer timeout. In order to handle this rare condition, interrupt status needs to be polled until interrupt is handled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200319212321.3297-2-digetx@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 25 additions and 0 deletions
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@ -24,6 +24,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include "dmaengine.h"
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#include "dmaengine.h"
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@ -202,6 +203,8 @@ struct tegra_dma_channel {
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unsigned int slave_id;
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unsigned int slave_id;
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struct dma_slave_config dma_sconfig;
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struct dma_slave_config dma_sconfig;
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struct tegra_dma_channel_regs channel_reg;
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struct tegra_dma_channel_regs channel_reg;
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struct wait_queue_head wq;
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};
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};
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/* tegra_dma: Tegra DMA specific information */
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/* tegra_dma: Tegra DMA specific information */
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@ -680,6 +683,7 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
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tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
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tdc->isr_handler(tdc, false);
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tdc->isr_handler(tdc, false);
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tasklet_schedule(&tdc->tasklet);
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tasklet_schedule(&tdc->tasklet);
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wake_up_all(&tdc->wq);
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spin_unlock(&tdc->lock);
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spin_unlock(&tdc->lock);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -785,6 +789,7 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
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tegra_dma_resume(tdc);
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tegra_dma_resume(tdc);
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pm_runtime_put(tdc->tdma->dev);
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pm_runtime_put(tdc->tdma->dev);
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wake_up_all(&tdc->wq);
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skip_dma_stop:
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skip_dma_stop:
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tegra_dma_abort_all(tdc);
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tegra_dma_abort_all(tdc);
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@ -800,10 +805,29 @@ skip_dma_stop:
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return 0;
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return 0;
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}
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}
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static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc)
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{
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unsigned long flags;
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u32 status;
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spin_lock_irqsave(&tdc->lock, flags);
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status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
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spin_unlock_irqrestore(&tdc->lock, flags);
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return !(status & TEGRA_APBDMA_STATUS_ISE_EOC);
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}
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static void tegra_dma_synchronize(struct dma_chan *dc)
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static void tegra_dma_synchronize(struct dma_chan *dc)
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{
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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/*
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* CPU, which handles interrupt, could be busy in
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* uninterruptible state, in this case sibling CPU
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* should wait until interrupt is handled.
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*/
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wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc));
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tasklet_kill(&tdc->tasklet);
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tasklet_kill(&tdc->tasklet);
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}
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}
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@ -1498,6 +1522,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
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tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
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tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
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(unsigned long)tdc);
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(unsigned long)tdc);
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spin_lock_init(&tdc->lock);
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spin_lock_init(&tdc->lock);
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init_waitqueue_head(&tdc->wq);
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INIT_LIST_HEAD(&tdc->pending_sg_req);
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INIT_LIST_HEAD(&tdc->pending_sg_req);
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INIT_LIST_HEAD(&tdc->free_sg_req);
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INIT_LIST_HEAD(&tdc->free_sg_req);
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