phy: freescale: add Samsung HDMI PHY
This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Based on downstream implementation from Sandor Yu <Sandor.yu@nxp.com>. According to the TRM, the PHY receives parallel data from the link and serializes it. It also sets the PLL clock needed for the TX serializer. Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Tested-by: Richard Leitner <richard.leitner@skidata.com> Co-developed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Link: https://lore.kernel.org/r/20240227220444.77566-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Lucas Stach
Vinod Koul
parent
d0f4b70eb9
commit
6ad082bee9
3 changed files with 727 additions and 0 deletions
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@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE
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Enable this to add support for the PCIE PHY as found on
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i.MX8M family of SOCs.
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config PHY_FSL_SAMSUNG_HDMI_PHY
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tristate "Samsung HDMI PHY support"
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depends on OF && HAS_IOMEM && COMMON_CLK
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help
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Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
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endif
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config PHY_FSL_LYNX_28G
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@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
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obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
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obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
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obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
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obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
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720
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
Normal file
720
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
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@ -0,0 +1,720 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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* Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#define PHY_REG_00 0x00
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#define PHY_REG_01 0x04
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#define PHY_REG_02 0x08
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#define PHY_REG_08 0x20
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#define PHY_REG_09 0x24
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#define PHY_REG_10 0x28
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#define PHY_REG_11 0x2c
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#define PHY_REG_12 0x30
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#define REG12_CK_DIV_MASK GENMASK(5, 4)
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#define PHY_REG_13 0x34
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#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
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#define PHY_REG_14 0x38
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#define REG14_TOL_MASK GENMASK(7, 4)
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#define REG14_RP_CODE_MASK GENMASK(3, 1)
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#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
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#define PHY_REG_15 0x3c
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#define PHY_REG_16 0x40
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#define PHY_REG_17 0x44
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#define PHY_REG_18 0x48
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#define PHY_REG_19 0x4c
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#define PHY_REG_20 0x50
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#define PHY_REG_21 0x54
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#define REG21_SEL_TX_CK_INV BIT(7)
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#define REG21_PMS_S_MASK GENMASK(3, 0)
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#define PHY_REG_22 0x58
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#define PHY_REG_23 0x5c
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#define PHY_REG_24 0x60
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#define PHY_REG_25 0x64
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#define PHY_REG_26 0x68
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#define PHY_REG_27 0x6c
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#define PHY_REG_28 0x70
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#define PHY_REG_29 0x74
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#define PHY_REG_30 0x78
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#define PHY_REG_31 0x7c
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#define PHY_REG_32 0x80
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/*
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* REG33 does not match the ref manual. According to Sandor Yu from NXP,
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* "There is a doc issue on the i.MX8MP latest RM"
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* REG33 is being used per guidance from Sandor
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*/
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#define PHY_REG_33 0x84
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#define REG33_MODE_SET_DONE BIT(7)
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#define REG33_FIX_DA BIT(1)
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#define PHY_REG_34 0x88
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#define REG34_PHY_READY BIT(7)
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#define REG34_PLL_LOCK BIT(6)
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#define REG34_PHY_CLK_READY BIT(5)
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#define PHY_REG_35 0x8c
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#define PHY_REG_36 0x90
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#define PHY_REG_37 0x94
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#define PHY_REG_38 0x98
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#define PHY_REG_39 0x9c
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#define PHY_REG_40 0xa0
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#define PHY_REG_41 0xa4
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#define PHY_REG_42 0xa8
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#define PHY_REG_43 0xac
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#define PHY_REG_44 0xb0
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#define PHY_REG_45 0xb4
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#define PHY_REG_46 0xb8
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#define PHY_REG_47 0xbc
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#define PHY_PLL_DIV_REGS_NUM 6
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struct phy_config {
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u32 pixclk;
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u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM];
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};
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static const struct phy_config phy_pll_cfg[] = {
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{
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.pixclk = 22250000,
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.pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 23750000,
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.pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
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}, {
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.pixclk = 24000000,
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.pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 24024000,
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.pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
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}, {
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.pixclk = 25175000,
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.pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
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}, {
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.pixclk = 25200000,
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.pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 26750000,
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.pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 27000000,
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.pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 27027000,
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.pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 29500000,
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.pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },
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}, {
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.pixclk = 30750000,
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.pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },
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}, {
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.pixclk = 30888000,
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.pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },
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}, {
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.pixclk = 33750000,
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.pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },
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}, {
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.pixclk = 35000000,
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.pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 36000000,
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.pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 36036000,
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.pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 40000000,
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.pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 43200000,
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.pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 43243200,
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.pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 44500000,
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.pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },
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}, {
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.pixclk = 47000000,
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.pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },
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}, {
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.pixclk = 47500000,
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.pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },
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}, {
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.pixclk = 50349650,
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.pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
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}, {
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.pixclk = 50400000,
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.pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 53250000,
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.pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
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}, {
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.pixclk = 53500000,
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.pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 54000000,
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.pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 54054000,
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.pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 59000000,
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.pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },
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}, {
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.pixclk = 59340659,
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.pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
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}, {
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.pixclk = 59400000,
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.pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 61500000,
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.pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
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}, {
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.pixclk = 63500000,
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.pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },
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}, {
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.pixclk = 67500000,
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.pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 },
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}, {
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.pixclk = 70000000,
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.pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 72000000,
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.pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 72072000,
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.pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 74176000,
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.pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 },
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}, {
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.pixclk = 74250000,
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.pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },
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}, {
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.pixclk = 78500000,
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.pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
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}, {
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.pixclk = 80000000,
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.pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 82000000,
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.pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
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}, {
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.pixclk = 82500000,
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.pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },
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}, {
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.pixclk = 89000000,
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.pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },
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}, {
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.pixclk = 90000000,
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.pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 },
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}, {
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.pixclk = 94000000,
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.pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },
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}, {
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.pixclk = 95000000,
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.pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 },
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}, {
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.pixclk = 98901099,
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.pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 },
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}, {
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.pixclk = 99000000,
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.pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },
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}, {
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.pixclk = 100699300,
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.pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
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}, {
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.pixclk = 100800000,
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.pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 102500000,
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.pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
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}, {
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.pixclk = 104750000,
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.pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },
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}, {
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.pixclk = 106500000,
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.pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },
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}, {
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.pixclk = 107000000,
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.pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
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}, {
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.pixclk = 108000000,
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.pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 108108000,
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.pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
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}, {
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.pixclk = 118000000,
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.pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
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}, {
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.pixclk = 118800000,
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.pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 123000000,
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.pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
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}, {
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.pixclk = 127000000,
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.pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 },
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}, {
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.pixclk = 135000000,
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.pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 },
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}, {
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.pixclk = 135580000,
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.pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b },
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}, {
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.pixclk = 137520000,
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.pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 },
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}, {
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.pixclk = 138750000,
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.pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d },
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}, {
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.pixclk = 140000000,
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.pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
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}, {
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.pixclk = 144000000,
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.pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 148352000,
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.pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
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}, {
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.pixclk = 148500000,
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.pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 },
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}, {
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.pixclk = 154000000,
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.pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 },
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}, {
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.pixclk = 157000000,
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.pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 },
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}, {
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.pixclk = 160000000,
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.pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 },
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}, {
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.pixclk = 162000000,
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.pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 },
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}, {
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.pixclk = 164000000,
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.pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b },
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}, {
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.pixclk = 165000000,
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.pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
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}, {
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.pixclk = 180000000,
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.pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },
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}, {
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.pixclk = 185625000,
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.pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
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}, {
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.pixclk = 188000000,
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.pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 },
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}, {
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.pixclk = 198000000,
|
||||
.pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 },
|
||||
}, {
|
||||
.pixclk = 205000000,
|
||||
.pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b },
|
||||
}, {
|
||||
.pixclk = 209500000,
|
||||
.pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 },
|
||||
}, {
|
||||
.pixclk = 213000000,
|
||||
.pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
|
||||
}, {
|
||||
.pixclk = 216000000,
|
||||
.pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },
|
||||
}, {
|
||||
.pixclk = 216216000,
|
||||
.pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
|
||||
}, {
|
||||
.pixclk = 237600000,
|
||||
.pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },
|
||||
}, {
|
||||
.pixclk = 254000000,
|
||||
.pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
|
||||
}, {
|
||||
.pixclk = 277500000,
|
||||
.pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
|
||||
}, {
|
||||
.pixclk = 288000000,
|
||||
.pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },
|
||||
}, {
|
||||
.pixclk = 297000000,
|
||||
.pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
|
||||
},
|
||||
};
|
||||
|
||||
struct reg_settings {
|
||||
u8 reg;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
static const struct reg_settings common_phy_cfg[] = {
|
||||
{ PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 },
|
||||
{ PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 },
|
||||
{ PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 },
|
||||
/* REG12 pixclk specific */
|
||||
/* REG13 pixclk specific */
|
||||
/* REG14 pixclk specific */
|
||||
{ PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c },
|
||||
{ PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 },
|
||||
{ PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 },
|
||||
/* REG21 pixclk specific */
|
||||
{ PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 },
|
||||
{ PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f },
|
||||
{ PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 },
|
||||
{ PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 },
|
||||
{ PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 },
|
||||
{ PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 },
|
||||
{ PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 },
|
||||
{ PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 },
|
||||
{ PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 },
|
||||
{ PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 },
|
||||
{ PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f },
|
||||
{ PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 },
|
||||
{ PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 }
|
||||
};
|
||||
|
||||
struct fsl_samsung_hdmi_phy {
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct clk *apbclk;
|
||||
struct clk *refclk;
|
||||
|
||||
/* clk provider */
|
||||
struct clk_hw hw;
|
||||
const struct phy_config *cur_cfg;
|
||||
};
|
||||
|
||||
static inline struct fsl_samsung_hdmi_phy *
|
||||
to_fsl_samsung_hdmi_phy(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
|
||||
}
|
||||
|
||||
static void
|
||||
fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy,
|
||||
const struct phy_config *cfg)
|
||||
{
|
||||
u8 div = 0x1;
|
||||
|
||||
switch (cfg->pixclk) {
|
||||
case 22250000 ... 33750000:
|
||||
div = 0xf;
|
||||
break;
|
||||
case 35000000 ... 40000000:
|
||||
div = 0xb;
|
||||
break;
|
||||
case 43200000 ... 47500000:
|
||||
div = 0x9;
|
||||
break;
|
||||
case 50349650 ... 63500000:
|
||||
div = 0x7;
|
||||
break;
|
||||
case 67500000 ... 90000000:
|
||||
div = 0x5;
|
||||
break;
|
||||
case 94000000 ... 148500000:
|
||||
div = 0x3;
|
||||
break;
|
||||
case 154000000 ... 297000000:
|
||||
div = 0x1;
|
||||
break;
|
||||
}
|
||||
|
||||
writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),
|
||||
phy->regs + PHY_REG_21);
|
||||
}
|
||||
|
||||
static void
|
||||
fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
|
||||
const struct phy_config *cfg)
|
||||
{
|
||||
u32 pclk = cfg->pixclk;
|
||||
u32 fld_tg_code;
|
||||
u32 pclk_khz;
|
||||
u8 div = 1;
|
||||
|
||||
switch (cfg->pixclk) {
|
||||
case 22250000 ... 47500000:
|
||||
div = 1;
|
||||
break;
|
||||
case 50349650 ... 99000000:
|
||||
div = 2;
|
||||
break;
|
||||
case 100699300 ... 198000000:
|
||||
div = 4;
|
||||
break;
|
||||
case 205000000 ... 297000000:
|
||||
div = 8;
|
||||
break;
|
||||
}
|
||||
|
||||
writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12);
|
||||
|
||||
/*
|
||||
* Calculation for the frequency lock detector target code (fld_tg_code)
|
||||
* is based on reference manual register description of PHY_REG13
|
||||
* (13.10.3.1.14.2):
|
||||
* 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV
|
||||
* 2nd) Increase resolution to avoid rounding issues
|
||||
* 3th) Do the div (256 / Freq. of int_pllclk) * 24
|
||||
* 4th) Reduce the resolution and always round up since the NXP
|
||||
* settings rounding up always too. TODO: Check if that is
|
||||
* correct.
|
||||
*/
|
||||
pclk /= div;
|
||||
pclk_khz = pclk / 1000;
|
||||
fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24;
|
||||
fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000);
|
||||
|
||||
/* FLD_TOL and FLD_RP_CODE taken from downstream driver */
|
||||
writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
|
||||
phy->regs + PHY_REG_13);
|
||||
writeb(FIELD_PREP(REG14_TOL_MASK, 2) |
|
||||
FIELD_PREP(REG14_RP_CODE_MASK, 2) |
|
||||
FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
|
||||
phy->regs + PHY_REG_14);
|
||||
}
|
||||
|
||||
static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
|
||||
const struct phy_config *cfg)
|
||||
{
|
||||
int i, ret;
|
||||
u8 val;
|
||||
|
||||
/* HDMI PHY init */
|
||||
writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
|
||||
|
||||
/* common PHY registers */
|
||||
for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
|
||||
writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);
|
||||
|
||||
/* set individual PLL registers PHY_REG2 ... PHY_REG7 */
|
||||
for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
|
||||
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4);
|
||||
|
||||
fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);
|
||||
fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
|
||||
|
||||
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33);
|
||||
|
||||
ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
|
||||
val & REG34_PLL_LOCK, 50, 20000);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "PLL failed to lock\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
|
||||
|
||||
if (!phy->cur_cfg)
|
||||
return 74250000;
|
||||
|
||||
return phy->cur_cfg->pixclk;
|
||||
}
|
||||
|
||||
static long phy_clk_round_rate(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long *parent_rate)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
|
||||
if (phy_pll_cfg[i].pixclk <= rate)
|
||||
return phy_pll_cfg[i].pixclk;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int phy_clk_set_rate(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
|
||||
if (phy_pll_cfg[i].pixclk <= rate)
|
||||
break;
|
||||
|
||||
if (i < 0)
|
||||
return -EINVAL;
|
||||
|
||||
phy->cur_cfg = &phy_pll_cfg[i];
|
||||
|
||||
return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
|
||||
}
|
||||
|
||||
static const struct clk_ops phy_clk_ops = {
|
||||
.recalc_rate = phy_clk_recalc_rate,
|
||||
.round_rate = phy_clk_round_rate,
|
||||
.set_rate = phy_clk_set_rate,
|
||||
};
|
||||
|
||||
static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
|
||||
{
|
||||
struct device *dev = phy->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct clk_init_data init;
|
||||
const char *parent_name;
|
||||
struct clk *phyclk;
|
||||
int ret;
|
||||
|
||||
parent_name = __clk_get_name(phy->refclk);
|
||||
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
init.name = "hdmi_pclk";
|
||||
init.ops = &phy_clk_ops;
|
||||
|
||||
phy->hw.init = &init;
|
||||
|
||||
phyclk = devm_clk_register(dev, &phy->hw);
|
||||
if (IS_ERR(phyclk))
|
||||
return dev_err_probe(dev, PTR_ERR(phyclk),
|
||||
"failed to register clock\n");
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret,
|
||||
"failed to register clock provider\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct fsl_samsung_hdmi_phy *phy;
|
||||
int ret;
|
||||
|
||||
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, phy);
|
||||
phy->dev = &pdev->dev;
|
||||
|
||||
phy->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(phy->regs))
|
||||
return PTR_ERR(phy->regs);
|
||||
|
||||
phy->apbclk = devm_clk_get(phy->dev, "apb");
|
||||
if (IS_ERR(phy->apbclk))
|
||||
return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
|
||||
"failed to get apb clk\n");
|
||||
|
||||
phy->refclk = devm_clk_get(phy->dev, "ref");
|
||||
if (IS_ERR(phy->refclk))
|
||||
return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
|
||||
"failed to get ref clk\n");
|
||||
|
||||
ret = clk_prepare_enable(phy->apbclk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "failed to enable apbclk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_get_noresume(phy->dev);
|
||||
pm_runtime_set_active(phy->dev);
|
||||
pm_runtime_enable(phy->dev);
|
||||
|
||||
ret = phy_clk_register(phy);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "register clk failed\n");
|
||||
goto register_clk_failed;
|
||||
}
|
||||
|
||||
pm_runtime_put(phy->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
register_clk_failed:
|
||||
clk_disable_unprepare(phy->apbclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev)
|
||||
{
|
||||
struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(phy->apbclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev)
|
||||
{
|
||||
struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(phy->apbclk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "failed to enable apbclk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (phy->cur_cfg)
|
||||
ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops,
|
||||
fsl_samsung_hdmi_phy_suspend,
|
||||
fsl_samsung_hdmi_phy_resume, NULL);
|
||||
|
||||
static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {
|
||||
{
|
||||
.compatible = "fsl,imx8mp-hdmi-phy",
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);
|
||||
|
||||
static struct platform_driver fsl_samsung_hdmi_phy_driver = {
|
||||
.probe = fsl_samsung_hdmi_phy_probe,
|
||||
.remove = fsl_samsung_hdmi_phy_remove,
|
||||
.driver = {
|
||||
.name = "fsl-samsung-hdmi-phy",
|
||||
.of_match_table = fsl_samsung_hdmi_phy_of_match,
|
||||
.pm = pm_ptr(&fsl_samsung_hdmi_phy_pm_ops),
|
||||
},
|
||||
};
|
||||
module_platform_driver(fsl_samsung_hdmi_phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
|
||||
MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Add table
Reference in a new issue