net: dsa: qca8k: move pcs configuration
Move the PCS configuration to qca8k_pcs_config(). Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King (Oracle)
David S. Miller
parent
9612a8f915
commit
7544b3ff74
1 changed files with 84 additions and 66 deletions
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@ -1706,8 +1706,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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const struct phylink_link_state *state)
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const struct phylink_link_state *state)
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{
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{
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struct qca8k_priv *priv = ds->priv;
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struct qca8k_priv *priv = ds->priv;
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int cpu_port_index, ret;
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int cpu_port_index;
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u32 reg, val;
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u32 reg;
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switch (port) {
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switch (port) {
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case 0: /* 1st CPU port */
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case 0: /* 1st CPU port */
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@ -1773,70 +1773,6 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_1000BASEX:
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/* Enable SGMII on the port */
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/* Enable SGMII on the port */
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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/* Enable/disable SerDes auto-negotiation as necessary */
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ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
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if (ret)
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return;
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if (phylink_autoneg_inband(mode))
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val &= ~QCA8K_PWS_SERDES_AEN_DIS;
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else
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val |= QCA8K_PWS_SERDES_AEN_DIS;
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qca8k_write(priv, QCA8K_REG_PWS, val);
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/* Configure the SGMII parameters */
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ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
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if (ret)
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return;
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val |= QCA8K_SGMII_EN_SD;
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if (priv->ports_config.sgmii_enable_pll)
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val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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QCA8K_SGMII_EN_TX;
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if (dsa_is_cpu_port(ds, port)) {
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/* CPU port, we're talking to the CPU MAC, be a PHY */
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_PHY;
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} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_MAC;
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} else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_BASEX;
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}
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qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
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/* From original code is reported port instability as SGMII also
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* require delay set. Apply advised values here or take them from DT.
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*/
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if (state->interface == PHY_INTERFACE_MODE_SGMII)
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qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
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* falling edge is set writing in the PORT0 PAD reg
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*/
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if (priv->switch_id == QCA8K_ID_QCA8327 ||
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priv->switch_id == QCA8K_ID_QCA8337)
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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val = 0;
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/* SGMII Clock phase configuration */
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if (priv->ports_config.sgmii_rx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
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if (priv->ports_config.sgmii_tx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
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if (val)
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ret = qca8k_rmw(priv, reg,
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QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
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QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
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val);
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break;
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break;
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default:
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default:
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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@ -1981,6 +1917,88 @@ static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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const unsigned long *advertising,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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bool permit_pause_to_mac)
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{
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{
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struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
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int cpu_port_index, ret, port;
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u32 reg, val;
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port = pcs_to_qca8k_pcs(pcs)->port;
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switch (port) {
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case 0:
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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cpu_port_index = QCA8K_CPU_PORT0;
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break;
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case 6:
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reg = QCA8K_REG_PORT6_PAD_CTRL;
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cpu_port_index = QCA8K_CPU_PORT6;
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break;
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default:
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WARN_ON(1);
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}
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/* Enable/disable SerDes auto-negotiation as necessary */
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ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
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if (ret)
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return ret;
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if (phylink_autoneg_inband(mode))
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val &= ~QCA8K_PWS_SERDES_AEN_DIS;
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else
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val |= QCA8K_PWS_SERDES_AEN_DIS;
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qca8k_write(priv, QCA8K_REG_PWS, val);
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/* Configure the SGMII parameters */
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ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
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if (ret)
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return ret;
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val |= QCA8K_SGMII_EN_SD;
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if (priv->ports_config.sgmii_enable_pll)
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val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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QCA8K_SGMII_EN_TX;
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if (dsa_is_cpu_port(priv->ds, port)) {
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/* CPU port, we're talking to the CPU MAC, be a PHY */
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_PHY;
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} else if (interface == PHY_INTERFACE_MODE_SGMII) {
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_MAC;
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} else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
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val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
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val |= QCA8K_SGMII_MODE_CTRL_BASEX;
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}
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qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
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/* From original code is reported port instability as SGMII also
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* require delay set. Apply advised values here or take them from DT.
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*/
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if (interface == PHY_INTERFACE_MODE_SGMII)
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qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
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* falling edge is set writing in the PORT0 PAD reg
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*/
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if (priv->switch_id == QCA8K_ID_QCA8327 ||
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priv->switch_id == QCA8K_ID_QCA8337)
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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val = 0;
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/* SGMII Clock phase configuration */
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if (priv->ports_config.sgmii_rx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
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if (priv->ports_config.sgmii_tx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
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if (val)
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ret = qca8k_rmw(priv, reg,
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QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
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QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
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val);
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return 0;
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return 0;
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}
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}
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