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ARM: dts: stm32: Add QSPI NOR on AV96

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The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Marek Vasut 2020-04-22 12:46:03 +02:00 • committed by Alexandre Torgue
parent 611325f681
commit 76045bc457
1 changed files with 20 additions and 0 deletions
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20
arch/arm/boot/dts/stm32mp157a-avenger96.dts
View file

@ -21,6 +21,7 @@
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
spi0 = &qspi;
};
chosen {
@ -314,6 +315,25 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&rng1 {
status = "okay";
};