i2c: amd-asf: Add i2c_algorithm operations to support AMD ASF with SMBus
Implement the i2c_algorithm operations to enable support for AMD ASF (Alert Standard Format) with SMBus. This enhancement includes: - Adding functionality to identify and select the supported ASF functions. - Implementing mechanisms for registering and deregistering I2C slave devices. - Providing support for data transfer operations over ASF. Additionally, include a 'select' Kconfig entry as the current patch utilizes .reg_slave() and .unreg_slave() callbacks, which are controlled by CONFIG_I2C_SLAVE. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Shyam Sundar S K
Andi Shyti
parent
c509ebdb95
commit
78a78b3215
2 changed files with 182 additions and 0 deletions
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@ -98,6 +98,7 @@ config I2C_AMD_MP2
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config I2C_AMD_ASF
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tristate "AMD ASF I2C Controller Support"
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depends on I2C_PIIX4
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select I2C_SLAVE
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help
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This option enables support for the AMD ASF (Alert Standard Format)
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I2C controller. The AMD ASF controller is an SMBus controller with
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@ -9,6 +9,7 @@
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* Sanket Goswami <Sanket.Goswami@amd.com>
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gfp_types.h>
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@ -22,12 +23,190 @@
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#include "i2c-piix4.h"
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/* ASF register bits */
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#define ASF_SLV_LISTN 0
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#define ASF_SLV_INTR 1
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#define ASF_SLV_RST 4
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#define ASF_PEC_SP 5
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#define ASF_DATA_EN 7
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#define ASF_MSTR_EN 16
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#define ASF_CLK_EN 17
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/* ASF address offsets */
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#define ASFLISADDR (0x09 + piix4_smba)
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#define ASFSTA (0x0A + piix4_smba)
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#define ASFSLVSTA (0x0D + piix4_smba)
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#define ASFDATABNKSEL (0x13 + piix4_smba)
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#define ASFSLVEN (0x15 + piix4_smba)
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#define ASF_BLOCK_MAX_BYTES 72
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struct amd_asf_dev {
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struct i2c_adapter adap;
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struct i2c_client *target;
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struct sb800_mmio_cfg mmio_cfg;
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struct resource *port_addr;
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};
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static void amd_asf_update_ioport_target(unsigned short piix4_smba, u8 bit,
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unsigned long offset, bool set)
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{
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unsigned long reg;
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reg = inb_p(offset);
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__assign_bit(bit, ®, set);
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outb_p(reg, offset);
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}
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static void amd_asf_update_mmio_target(struct amd_asf_dev *dev, u8 bit, bool set)
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{
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unsigned long reg;
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reg = ioread32(dev->mmio_cfg.addr);
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__assign_bit(bit, ®, set);
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iowrite32(reg, dev->mmio_cfg.addr);
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}
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static void amd_asf_setup_target(struct amd_asf_dev *dev)
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{
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unsigned short piix4_smba = dev->port_addr->start;
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/* Reset both host and target before setting up */
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outb_p(0, SMBHSTSTS);
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outb_p(0, ASFSLVSTA);
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outb_p(0, ASFSTA);
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/* Update target address */
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_LISTN, ASFLISADDR, true);
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/* Enable target and set the clock */
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amd_asf_update_mmio_target(dev, ASF_MSTR_EN, false);
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amd_asf_update_mmio_target(dev, ASF_CLK_EN, true);
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/* Enable target interrupt */
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_INTR, ASFSLVEN, true);
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_RST, ASFSLVEN, false);
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/* Enable PEC and PEC append */
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amd_asf_update_ioport_target(piix4_smba, ASF_DATA_EN, SMBHSTCNT, true);
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amd_asf_update_ioport_target(piix4_smba, ASF_PEC_SP, SMBHSTCNT, true);
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}
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static int amd_asf_access(struct i2c_adapter *adap, u16 addr, u8 command, u8 *data)
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{
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struct amd_asf_dev *dev = i2c_get_adapdata(adap);
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unsigned short piix4_smba = dev->port_addr->start;
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u8 i, len;
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outb_p((addr << 1), SMBHSTADD);
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outb_p(command, SMBHSTCMD);
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len = data[0];
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if (len == 0 || len > ASF_BLOCK_MAX_BYTES)
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return -EINVAL;
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outb_p(len, SMBHSTDAT0);
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/* Reset SMBBLKDAT */
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inb_p(SMBHSTCNT);
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for (i = 1; i <= len; i++)
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outb_p(data[i], SMBBLKDAT);
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outb_p(PIIX4_BLOCK_DATA, SMBHSTCNT);
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/* Enable PEC and PEC append */
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amd_asf_update_ioport_target(piix4_smba, ASF_DATA_EN, SMBHSTCNT, true);
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amd_asf_update_ioport_target(piix4_smba, ASF_PEC_SP, SMBHSTCNT, true);
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return piix4_transaction(adap, piix4_smba);
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}
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static int amd_asf_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct amd_asf_dev *dev = i2c_get_adapdata(adap);
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unsigned short piix4_smba = dev->port_addr->start;
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u8 asf_data[ASF_BLOCK_MAX_BYTES];
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struct i2c_msg *dev_msgs = msgs;
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u8 prev_port;
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int ret;
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if (msgs->flags & I2C_M_RD) {
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dev_err(&adap->dev, "ASF: Read not supported\n");
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return -EOPNOTSUPP;
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}
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/* Exclude the receive header and PEC */
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if (msgs->len > ASF_BLOCK_MAX_BYTES - 3) {
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dev_warn(&adap->dev, "ASF: max message length exceeded\n");
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return -EOPNOTSUPP;
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}
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asf_data[0] = dev_msgs->len;
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memcpy(asf_data + 1, dev_msgs[0].buf, dev_msgs->len);
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ret = piix4_sb800_region_request(&adap->dev, &dev->mmio_cfg);
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if (ret)
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return ret;
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_RST, ASFSLVEN, true);
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_LISTN, ASFLISADDR, false);
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/* Clear ASF target status */
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outb_p(0, ASFSLVSTA);
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/* Enable ASF SMBus controller function */
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amd_asf_update_mmio_target(dev, ASF_MSTR_EN, true);
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prev_port = piix4_sb800_port_sel(0, &dev->mmio_cfg);
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ret = amd_asf_access(adap, msgs->addr, msgs[0].buf[0], asf_data);
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piix4_sb800_port_sel(prev_port, &dev->mmio_cfg);
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amd_asf_setup_target(dev);
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piix4_sb800_region_release(&adap->dev, &dev->mmio_cfg);
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return ret;
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}
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static int amd_asf_reg_target(struct i2c_client *target)
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{
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struct amd_asf_dev *dev = i2c_get_adapdata(target->adapter);
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unsigned short piix4_smba = dev->port_addr->start;
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int ret;
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u8 reg;
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if (dev->target)
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return -EBUSY;
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ret = piix4_sb800_region_request(&target->dev, &dev->mmio_cfg);
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if (ret)
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return ret;
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reg = (target->addr << 1) | I2C_M_RD;
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outb_p(reg, ASFLISADDR);
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amd_asf_setup_target(dev);
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dev->target = target;
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amd_asf_update_ioport_target(piix4_smba, ASF_DATA_EN, ASFDATABNKSEL, false);
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piix4_sb800_region_release(&target->dev, &dev->mmio_cfg);
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return 0;
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}
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static int amd_asf_unreg_target(struct i2c_client *target)
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{
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struct amd_asf_dev *dev = i2c_get_adapdata(target->adapter);
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unsigned short piix4_smba = dev->port_addr->start;
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_INTR, ASFSLVEN, false);
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amd_asf_update_ioport_target(piix4_smba, ASF_SLV_RST, ASFSLVEN, true);
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dev->target = NULL;
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return 0;
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}
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static u32 amd_asf_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
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I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_PEC | I2C_FUNC_SLAVE;
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}
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static const struct i2c_algorithm amd_asf_smbus_algorithm = {
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.master_xfer = amd_asf_xfer,
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.reg_slave = amd_asf_reg_target,
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.unreg_slave = amd_asf_unreg_target,
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.functionality = amd_asf_func,
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};
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static int amd_asf_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -43,6 +222,7 @@ static int amd_asf_probe(struct platform_device *pdev)
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return dev_err_probe(dev, -EINVAL, "missing IO resources\n");
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asf_dev->adap.owner = THIS_MODULE;
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asf_dev->adap.algo = &amd_asf_smbus_algorithm;
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asf_dev->adap.dev.parent = dev;
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i2c_set_adapdata(&asf_dev->adap, asf_dev);
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@ -66,5 +246,6 @@ static struct platform_driver amd_asf_driver = {
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};
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module_platform_driver(amd_asf_driver);
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MODULE_IMPORT_NS(PIIX4_SMBUS);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("AMD Alert Standard Format Driver");
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