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clk: mediatek: Fix asymmetrical PLL enable and disable control

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In fact, the en_mask is a combination of divider enable mask
and pll enable bit(bit0).
Before this patch, we enabled both divider mask and bit0 in prepare(),
but only cleared the bit0 in unprepare().
In the future, we hope en_mask will only be used as divider enable mask.
The enable register(CON0) will be set in 2 steps:
first is divider mask, and then bit0 during prepare(), and vice versa.
But considering backward compatibility, at this stage we allow en_mask
to be a combination or a pure divider enable mask.
And then we will make en_mask a pure divider enable mask in another
following patch series.

Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chun-Jie Chen 2021-07-26 18:57:04 +08:00 • committed by Stephen Boyd
parent 197ee5436b
commit 7cc4e1bbe3
1 changed files with 16 additions and 4 deletions
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20
drivers/clk/mediatek/clk-pll.c
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@ -238,6 +238,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
{ {
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r; u32 r;
u32 div_en_mask;
r = readl(pll->pwr_addr) | CON0_PWR_ON; r = readl(pll->pwr_addr) | CON0_PWR_ON;
writel(r, pll->pwr_addr); writel(r, pll->pwr_addr);
@ -247,10 +248,15 @@ static int mtk_pll_prepare(struct clk_hw *hw)
writel(r, pll->pwr_addr); writel(r, pll->pwr_addr);
udelay(1); udelay(1);
r = readl(pll->base_addr + REG_CON0); r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
r |= pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0); writel(r, pll->base_addr + REG_CON0);
div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
if (div_en_mask) {
r = readl(pll->base_addr + REG_CON0) | div_en_mask;
writel(r, pll->base_addr + REG_CON0);
}
__mtk_pll_tuner_enable(pll); __mtk_pll_tuner_enable(pll);
udelay(20); udelay(20);
@ -268,6 +274,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
{ {
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r; u32 r;
u32 div_en_mask;
if (pll->data->flags & HAVE_RST_BAR) { if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0); r = readl(pll->base_addr + REG_CON0);
@ -277,8 +284,13 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
__mtk_pll_tuner_disable(pll); __mtk_pll_tuner_disable(pll);
r = readl(pll->base_addr + REG_CON0); div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
r &= ~CON0_BASE_EN; if (div_en_mask) {
r = readl(pll->base_addr + REG_CON0) & ~div_en_mask;
writel(r, pll->base_addr + REG_CON0);
}
r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;
writel(r, pll->base_addr + REG_CON0); writel(r, pll->base_addr + REG_CON0);
r = readl(pll->pwr_addr) | CON0_ISO_EN; r = readl(pll->pwr_addr) | CON0_ISO_EN;