niansa-misc/linux
1
0
Fork 0
mirror of synced 2025-03-06 20:59:54 +01:00
Code Issues Projects Releases Packages Wiki Activity

drm fixes for 6.14-rc2

Browse source 
amdgpu:
 - Add new tiling flag for DCC write compress disable
 - Add BO metadata flag for DCC
 - Fix potential out of bounds access in display
 - Seamless boot fix
 - CONFIG_FRAME_WARN fix
 - PSR1 fix
 
 xe:
 - OA uAPI related fixes
 - Fix SRIOV migration initialization
 - Restore devcoredump to a sane state
 
 i915:
 - Fix the build error with clamp after WARN_ON on gcc 13.x+
 - HDCP related fixes
 - PMU fix zero delta busyness issue
 - Fix page cleanup on DMA remap failure
 - Drop 64bpp YUV formats from ICL+ SDR planes
 - GuC log related fix
 - DisplayPort related fixes
 
 ivpu:
 - Fix error handling
 
 komeda:
 - add return check
 
 zynqmp:
 - fix locking in DP code
 
 ast:
 - fix AST DP timeout
 
 cec:
 - fix broken CEC adapter check
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmemX5QACgkQDHTzWXnE
 hr5aqw//WDuUZG9yGh6+jXynDn7onKMQVRRdYzexkMTylOADCVtSg1XQiIyrhoSP
 Wu/l/CTapeqLfaWV0uDhz8vRncBj1HSGmaOH/dXS9z3J+O3ie+R+COhVzrLQEqlX
 Eu06Z+WrtQDl4qda2azIoMnRYZwHQmhxzTb9IBsqHb7GXrJ2YFTNT9QwcvOxVIBJ
 jyj68CoHuDmSJZKRWJ5eVwIY9twP/1dZQsNZihGQ/ICNQQ6muYZBPMOk6lbEN30e
 SSIcJkUcUWCtq6fQR8peiCTWCp8265IV23Waqh0UkUjHSbkyYhC8akk+pweoh+pv
 ChUNSwSofJVaax7FEw12AhlmKI/rYjhAmxtXV1Qpeyy4yW04RnsvKSEDnGZ9/Cek
 fflBbs8CayBfTe8URm/DGk8qUixkzOHA5tZk3nQ54nrMQQOpEkkUrbqGrkFUeVaC
 CtmkaiUfFtf/yfuLhZypstiWHon4FwvyWNo+QWbItpD01IPPHGlz1bbHVvgpluRi
 pcWRKRlwj1WyBAxhT+jjn5Hu50yIuivbiBHkeMUiKL03kBvMuplW+WiHIO4kMqj8
 5c7fEelcH5onM8oSTzs0s4QWCjjLLscvkMkkhIh0ot1mDJSR0SfBNiq6QDt7PpPf
 mjR9UMPLnLQJ/FN5Fz4j/+fd85ckG6ooWypgpyA4iyOiVITykeY=
 =/5Ke
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Just regular drm fixes, amdgpu, xe and i915 mostly, but a few
  scattered fixes. I think one of the i915 fixes fixes some build combos
  that Guenter was seeing.

  amdgpu:
   - Add new tiling flag for DCC write compress disable
   - Add BO metadata flag for DCC
   - Fix potential out of bounds access in display
   - Seamless boot fix
   - CONFIG_FRAME_WARN fix
   - PSR1 fix

  xe:
   - OA uAPI related fixes
   - Fix SRIOV migration initialization
   - Restore devcoredump to a sane state

  i915:
   - Fix the build error with clamp after WARN_ON on gcc 13.x+
   - HDCP related fixes
   - PMU fix zero delta busyness issue
   - Fix page cleanup on DMA remap failure
   - Drop 64bpp YUV formats from ICL+ SDR planes
   - GuC log related fix
   - DisplayPort related fixes

  ivpu:
   - Fix error handling

  komeda:
   - add return check

  zynqmp:
   - fix locking in DP code

  ast:
   - fix AST DP timeout

  cec:
   - fix broken CEC adapter check"

* tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel: (29 commits)
  drm/i915/dp: Fix potential infinite loop in 128b/132b SST
  Revert "drm/amd/display: Use HW lock mgr for PSR1"
  drm/amd/display: Respect user's CONFIG_FRAME_WARN more for dml files
  accel/amdxdna: Add MODULE_FIRMWARE() declarations
  drm/i915/dp: Iterate DSC BPP from high to low on all platforms
  drm/xe: Fix and re-enable xe_print_blob_ascii85()
  drm/xe/devcoredump: Move exec queue snapshot to Contexts section
  drm/xe/oa: Set stream->pollin in xe_oa_buffer_check_unlocked
  drm/xe/pf: Fix migration initialization
  drm/xe/oa: Preserve oa_ctrl unused bits
  drm/amd/display: Fix seamless boot sequence
  drm/amd/display: Fix out-of-bound accesses
  drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan
  drm/i915/backlight: Return immediately when scale() finds invalid parameters
  drm/i915/dp: Return min bpc supported by source instead of 0
  drm/i915/dp: fix the Adaptive sync Operation mode for SDP
  drm/i915/guc: Debug print LRC state entries only if the context is pinned
  drm/i915: Drop 64bpp YUV formats from ICL+ SDR planes
  drm/i915: Fix page cleanup on DMA remap failure
  drm/i915/pmu: Fix zero delta busyness issue
  ...
This commit is contained in:
Linus Torvalds 2025-02-07 12:21:54 -08:00
commit 7ee983c850
41 changed files with 250 additions and 149 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/accel/amdxdna/amdxdna_pci_drv.c
View file

@ -21,6 +21,11 @@
#define AMDXDNA_AUTOSUSPEND_DELAY 5000 /* milliseconds */ #define AMDXDNA_AUTOSUSPEND_DELAY 5000 /* milliseconds */
MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
/* /*
* Bind the driver base on (vendor_id, device_id) pair and later use the * Bind the driver base on (vendor_id, device_id) pair and later use the
* (device_id, rev_id) pair as a key to select the devices. The devices with * (device_id, rev_id) pair as a key to select the devices. The devices with

8
drivers/accel/ivpu/ivpu_drv.c
View file

@ -397,15 +397,19 @@ int ivpu_boot(struct ivpu_device *vdev)
if (ivpu_fw_is_cold_boot(vdev)) { if (ivpu_fw_is_cold_boot(vdev)) {
ret = ivpu_pm_dct_init(vdev); ret = ivpu_pm_dct_init(vdev);
if (ret) if (ret)
goto err_diagnose_failure; goto err_disable_ipc;
ret = ivpu_hw_sched_init(vdev); ret = ivpu_hw_sched_init(vdev);
if (ret) if (ret)
goto err_diagnose_failure; goto err_disable_ipc;
} }
return 0; return 0;
err_disable_ipc:
ivpu_ipc_disable(vdev);
ivpu_hw_irq_disable(vdev);
disable_irq(vdev->irq);
err_diagnose_failure: err_diagnose_failure:
ivpu_hw_diagnose_failure(vdev); ivpu_hw_diagnose_failure(vdev);
ivpu_mmu_evtq_dump(vdev); ivpu_mmu_evtq_dump(vdev);

84
drivers/accel/ivpu/ivpu_pm.c
View file

@ -115,41 +115,57 @@ err_power_down:
return ret; return ret;
} }
static void ivpu_pm_recovery_work(struct work_struct *work) static void ivpu_pm_reset_begin(struct ivpu_device *vdev)
{ {
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work); pm_runtime_disable(vdev->drm.dev);
struct ivpu_device *vdev = pm->vdev;
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
int ret;
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
ret = pm_runtime_resume_and_get(vdev->drm.dev);
if (ret)
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
ivpu_jsm_state_dump(vdev);
ivpu_dev_coredump(vdev);
atomic_inc(&vdev->pm->reset_counter); atomic_inc(&vdev->pm->reset_counter);
atomic_set(&vdev->pm->reset_pending, 1); atomic_set(&vdev->pm->reset_pending, 1);
down_write(&vdev->pm->reset_lock); down_write(&vdev->pm->reset_lock);
}
static void ivpu_pm_reset_complete(struct ivpu_device *vdev)
{
int ret;
ivpu_suspend(vdev);
ivpu_pm_prepare_cold_boot(vdev); ivpu_pm_prepare_cold_boot(vdev);
ivpu_jobs_abort_all(vdev); ivpu_jobs_abort_all(vdev);
ivpu_ms_cleanup_all(vdev); ivpu_ms_cleanup_all(vdev);
ret = ivpu_resume(vdev); ret = ivpu_resume(vdev);
if (ret) if (ret) {
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret); ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
pm_runtime_set_suspended(vdev->drm.dev);
} else {
pm_runtime_set_active(vdev->drm.dev);
}
up_write(&vdev->pm->reset_lock); up_write(&vdev->pm->reset_lock);
atomic_set(&vdev->pm->reset_pending, 0); atomic_set(&vdev->pm->reset_pending, 0);
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
pm_runtime_mark_last_busy(vdev->drm.dev); pm_runtime_mark_last_busy(vdev->drm.dev);
pm_runtime_put_autosuspend(vdev->drm.dev); pm_runtime_enable(vdev->drm.dev);
}
static void ivpu_pm_recovery_work(struct work_struct *work)
{
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
struct ivpu_device *vdev = pm->vdev;
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
ivpu_pm_reset_begin(vdev);
if (!pm_runtime_status_suspended(vdev->drm.dev)) {
ivpu_jsm_state_dump(vdev);
ivpu_dev_coredump(vdev);
ivpu_suspend(vdev);
}
ivpu_pm_reset_complete(vdev);
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
} }
void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason) void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
@ -309,7 +325,10 @@ int ivpu_rpm_get(struct ivpu_device *vdev)
int ret; int ret;
ret = pm_runtime_resume_and_get(vdev->drm.dev); ret = pm_runtime_resume_and_get(vdev->drm.dev);
drm_WARN_ON(&vdev->drm, ret < 0); if (ret < 0) {
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
pm_runtime_set_suspended(vdev->drm.dev);
}
return ret; return ret;
} }
@ -325,16 +344,13 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev)
struct ivpu_device *vdev = pci_get_drvdata(pdev); struct ivpu_device *vdev = pci_get_drvdata(pdev);
ivpu_dbg(vdev, PM, "Pre-reset..\n"); ivpu_dbg(vdev, PM, "Pre-reset..\n");
atomic_inc(&vdev->pm->reset_counter);
atomic_set(&vdev->pm->reset_pending, 1);
pm_runtime_get_sync(vdev->drm.dev); ivpu_pm_reset_begin(vdev);
down_write(&vdev->pm->reset_lock);
ivpu_prepare_for_reset(vdev); if (!pm_runtime_status_suspended(vdev->drm.dev)) {
ivpu_hw_reset(vdev); ivpu_prepare_for_reset(vdev);
ivpu_pm_prepare_cold_boot(vdev); ivpu_hw_reset(vdev);
ivpu_jobs_abort_all(vdev); }
ivpu_ms_cleanup_all(vdev);
ivpu_dbg(vdev, PM, "Pre-reset done.\n"); ivpu_dbg(vdev, PM, "Pre-reset done.\n");
} }
@ -342,18 +358,12 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev)
void ivpu_pm_reset_done_cb(struct pci_dev *pdev) void ivpu_pm_reset_done_cb(struct pci_dev *pdev)
{ {
struct ivpu_device *vdev = pci_get_drvdata(pdev); struct ivpu_device *vdev = pci_get_drvdata(pdev);
int ret;
ivpu_dbg(vdev, PM, "Post-reset..\n"); ivpu_dbg(vdev, PM, "Post-reset..\n");
ret = ivpu_resume(vdev);
if (ret)
ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
up_write(&vdev->pm->reset_lock);
atomic_set(&vdev->pm->reset_pending, 0);
ivpu_dbg(vdev, PM, "Post-reset done.\n");
pm_runtime_mark_last_busy(vdev->drm.dev); ivpu_pm_reset_complete(vdev);
pm_runtime_put_autosuspend(vdev->drm.dev);
ivpu_dbg(vdev, PM, "Post-reset done.\n");
} }
void ivpu_pm_init(struct ivpu_device *vdev) void ivpu_pm_init(struct ivpu_device *vdev)

3
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -119,9 +119,10 @@
* - 3.57.0 - Compute tunneling on GFX10+ * - 3.57.0 - Compute tunneling on GFX10+
* - 3.58.0 - Add GFX12 DCC support * - 3.58.0 - Add GFX12 DCC support
* - 3.59.0 - Cleared VRAM * - 3.59.0 - Cleared VRAM
* - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
*/ */
#define KMS_DRIVER_MAJOR 3 #define KMS_DRIVER_MAJOR 3
#define KMS_DRIVER_MINOR 59 #define KMS_DRIVER_MINOR 60
#define KMS_DRIVER_PATCHLEVEL 0 #define KMS_DRIVER_PATCHLEVEL 0
/* /*

8
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View file

@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
mutex_lock(&adev->mman.gtt_window_lock); mutex_lock(&adev->mman.gtt_window_lock);
while (src_mm.remaining) { while (src_mm.remaining) {
uint64_t from, to, cur_size, tiling_flags; uint64_t from, to, cur_size, tiling_flags;
uint32_t num_type, data_format, max_com; uint32_t num_type, data_format, max_com, write_compress_disable;
struct dma_fence *next; struct dma_fence *next;
/* Never copy more than 256MiB at once to avoid a timeout */ /* Never copy more than 256MiB at once to avoid a timeout */
@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
write_compress_disable =
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) | copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) | AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format)); AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
write_compress_disable));
} }
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv, r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
View file

@ -119,6 +119,8 @@ struct amdgpu_copy_mem {
#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f #define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
#define AMDGPU_COPY_FLAGS_SET(field, value) \ #define AMDGPU_COPY_FLAGS_SET(field, value) \
(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT) (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

5
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
View file

@ -1741,11 +1741,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
uint32_t byte_count, uint32_t byte_count,
uint32_t copy_flags) uint32_t copy_flags)
{ {
uint32_t num_type, data_format, max_com; uint32_t num_type, data_format, max_com, write_cm;
max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED); max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT); data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE); num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
@ -1762,7 +1763,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED))) if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) | ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) | ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
else else
ib->ptr[ib->length_dw++] = 0; ib->ptr[ib->length_dw++] = 0;

2
drivers/gpu/drm/amd/display/dc/core/dc.c
View file

@ -2133,7 +2133,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
dc_enable_stereo(dc, context, dc_streams, context->stream_count); dc_enable_stereo(dc, context, dc_streams, context->stream_count);
if (context->stream_count > get_seamless_boot_stream_count(context) || if (get_seamless_boot_stream_count(context) == 0 ||
context->stream_count == 0) { context->stream_count == 0) {
/* Must wait for no flips to be pending before doing optimize bw */ /* Must wait for no flips to be pending before doing optimize bw */
hwss_wait_for_no_pipes_pending(dc, context); hwss_wait_for_no_pipes_pending(dc, context);

3
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
View file

@ -63,8 +63,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
bool should_use_dmub_lock(struct dc_link *link) bool should_use_dmub_lock(struct dc_link *link)
{ {
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
link->psr_settings.psr_version == DC_PSR_VERSION_1)
return true; return true;
if (link->replay_settings.replay_feature_enabled) if (link->replay_settings.replay_feature_enabled)

14
drivers/gpu/drm/amd/display/dc/dml/Makefile
View file

@ -29,11 +29,15 @@ dml_ccflags := $(CC_FLAGS_FPU)
dml_rcflags := $(CC_FLAGS_NO_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU)
ifneq ($(CONFIG_FRAME_WARN),0) ifneq ($(CONFIG_FRAME_WARN),0)
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
frame_warn_flag := -Wframe-larger-than=3072 frame_warn_limit := 3072
else else
frame_warn_flag := -Wframe-larger-than=2048 frame_warn_limit := 2048
endif endif
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
endif
endif endif
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)

22
drivers/gpu/drm/amd/display/dc/dml2/Makefile
View file

@ -28,15 +28,19 @@ dml2_ccflags := $(CC_FLAGS_FPU)
dml2_rcflags := $(CC_FLAGS_NO_FPU) dml2_rcflags := $(CC_FLAGS_NO_FPU)
ifneq ($(CONFIG_FRAME_WARN),0) ifneq ($(CONFIG_FRAME_WARN),0)
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
frame_warn_flag := -Wframe-larger-than=4096 frame_warn_limit := 4096
else else
frame_warn_flag := -Wframe-larger-than=3072 frame_warn_limit := 3072
endif endif
else else
frame_warn_flag := -Wframe-larger-than=2048 frame_warn_limit := 2048
endif endif
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
endif
endif endif
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2

4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
View file

@ -1017,7 +1017,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
if (disp_cfg_stream_location < 0) if (disp_cfg_stream_location < 0)
disp_cfg_stream_location = dml_dispcfg->num_streams++; disp_cfg_stream_location = dml_dispcfg->num_streams++;
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx); populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);
adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]); adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);
populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]); populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);
@ -1042,7 +1042,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
if (disp_cfg_plane_location < 0) if (disp_cfg_plane_location < 0)
disp_cfg_plane_location = dml_dispcfg->num_planes++; disp_cfg_plane_location = dml_dispcfg->num_planes++;
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]); populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);
populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index); populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);

6
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
View file

@ -786,7 +786,7 @@ static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *
case SIGNAL_TYPE_DISPLAY_PORT_MST: case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT:
out->OutputEncoder[location] = dml_dp; out->OutputEncoder[location] = dml_dp;
if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1) if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0; out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
break; break;
case SIGNAL_TYPE_EDP: case SIGNAL_TYPE_EDP:
@ -1343,7 +1343,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
if (disp_cfg_stream_location < 0) if (disp_cfg_stream_location < 0)
disp_cfg_stream_location = dml_dispcfg->num_timings++; disp_cfg_stream_location = dml_dispcfg->num_timings++;
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]); populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2); populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
@ -1383,7 +1383,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
if (disp_cfg_plane_location < 0) if (disp_cfg_plane_location < 0)
disp_cfg_plane_location = dml_dispcfg->num_surfaces++; disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]); populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
populate_dml_plane_cfg_from_plane_state( populate_dml_plane_cfg_from_plane_state(

3
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
View file

@ -129,7 +129,8 @@ bool hubbub3_program_watermarks(
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF); DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
return wm_pending; return wm_pending;
} }

3
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
View file

@ -750,7 +750,8 @@ static bool hubbub31_program_watermarks(
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
return wm_pending; return wm_pending;
} }

3
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
View file

@ -786,7 +786,8 @@ static bool hubbub32_program_watermarks(
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

3
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
View file

@ -326,7 +326,8 @@ static bool hubbub35_program_watermarks(
DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/ DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/
REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

2
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
View file

@ -500,6 +500,8 @@ void hubp3_init(struct hubp *hubp)
//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
REG_WRITE(HUBPREQ_DEBUG, 1 << 26); REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);
hubp_reset(hubp); hubp_reset(hubp);
} }

2
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
View file

@ -168,6 +168,8 @@ void hubp32_init(struct hubp *hubp)
{ {
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);
} }
static struct hubp_funcs dcn32_hubp_funcs = { static struct hubp_funcs dcn32_hubp_funcs = {
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,

3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View file

@ -236,7 +236,8 @@ void dcn35_init_hw(struct dc *dc)
} }
hws->funcs.init_pipes(dc, dc->current_state); hws->funcs.init_pipes(dc, dc->current_state);
if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) if (dc->res_pool->hubbub->funcs->allow_self_refresh_control &&
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter)
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
} }

4
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
View file

@ -160,6 +160,10 @@ static int komeda_wb_connector_add(struct komeda_kms_dev *kms,
formats = komeda_get_layer_fourcc_list(&mdev->fmt_tbl, formats = komeda_get_layer_fourcc_list(&mdev->fmt_tbl,
kwb_conn->wb_layer->layer_type, kwb_conn->wb_layer->layer_type,
&n_formats); &n_formats);
if (!formats) {
kfree(kwb_conn);
return -ENOMEM;
}
err = drm_writeback_connector_init(&kms->base, wb_conn, err = drm_writeback_connector_init(&kms->base, wb_conn,
&komeda_wb_connector_funcs, &komeda_wb_connector_funcs,

2
drivers/gpu/drm/ast/ast_dp.c
View file

@ -195,7 +195,7 @@ static bool __ast_dp_wait_enable(struct ast_device *ast, bool enabled)
if (enabled) if (enabled)
vgacrdf_test |= AST_IO_VGACRDF_DP_VIDEO_ENABLE; vgacrdf_test |= AST_IO_VGACRDF_DP_VIDEO_ENABLE;
for (i = 0; i < 200; ++i) { for (i = 0; i < 1000; ++i) {
if (i) if (i)
mdelay(1); mdelay(1);
vgacrdf = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xdf, vgacrdf = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xdf,

14
drivers/gpu/drm/display/drm_dp_cec.c
View file

@ -311,16 +311,6 @@ void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address)
if (!aux->transfer) if (!aux->transfer)
return; return;
#ifndef CONFIG_MEDIA_CEC_RC
/*
* CEC_CAP_RC is part of CEC_CAP_DEFAULTS, but it is stripped by
* cec_allocate_adapter() if CONFIG_MEDIA_CEC_RC is undefined.
*
* Do this here as well to ensure the tests against cec_caps are
* correct.
*/
cec_caps &= ~CEC_CAP_RC;
#endif
cancel_delayed_work_sync(&aux->cec.unregister_work); cancel_delayed_work_sync(&aux->cec.unregister_work);
mutex_lock(&aux->cec.lock); mutex_lock(&aux->cec.lock);
@ -337,7 +327,9 @@ void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address)
num_las = CEC_MAX_LOG_ADDRS; num_las = CEC_MAX_LOG_ADDRS;
if (aux->cec.adap) { if (aux->cec.adap) {
if (aux->cec.adap->capabilities == cec_caps && /* Check if the adapter properties have changed */
if ((aux->cec.adap->capabilities & CEC_CAP_MONITOR_ALL) ==
(cec_caps & CEC_CAP_MONITOR_ALL) &&
aux->cec.adap->available_log_addrs == num_las) { aux->cec.adap->available_log_addrs == num_las) {
/* Unchanged, so just set the phys addr */ /* Unchanged, so just set the phys addr */
cec_s_phys_addr(aux->cec.adap, source_physical_address, false); cec_s_phys_addr(aux->cec.adap, source_physical_address, false);

5
drivers/gpu/drm/i915/display/intel_backlight.c
View file

@ -41,8 +41,9 @@ static u32 scale(u32 source_val,
{ {
u64 target_val; u64 target_val;
WARN_ON(source_min > source_max); if (WARN_ON(source_min >= source_max) ||
WARN_ON(target_min > target_max); WARN_ON(target_min > target_max))
return target_min;
/* defensive */ /* defensive */
source_val = clamp(source_val, source_min, source_max); source_val = clamp(source_val, source_min, source_max);

12
drivers/gpu/drm/i915/display/intel_dp.c
View file

@ -1791,7 +1791,7 @@ int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
if (DISPLAY_VER(display) == 11) if (DISPLAY_VER(display) == 11)
return 10; return 10;
return 0; return intel_dp_dsc_min_src_input_bpc();
} }
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
@ -2072,11 +2072,10 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
/* Compressed BPP should be less than the Input DSC bpp */ /* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) {
if (valid_dsc_bpp[i] < dsc_min_bpp) if (valid_dsc_bpp[i] < dsc_min_bpp ||
valid_dsc_bpp[i] > dsc_max_bpp)
continue; continue;
if (valid_dsc_bpp[i] > dsc_max_bpp)
break;
ret = dsc_compute_link_config(intel_dp, ret = dsc_compute_link_config(intel_dp,
pipe_config, pipe_config,
@ -2829,7 +2828,6 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
as_sdp->length = 0x9; as_sdp->length = 0x9;
as_sdp->duration_incr_ms = 0; as_sdp->duration_incr_ms = 0;
@ -2840,7 +2838,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
as_sdp->target_rr_divider = true; as_sdp->target_rr_divider = true;
} else { } else {
as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
as_sdp->vtotal = adjusted_mode->vtotal; as_sdp->vtotal = adjusted_mode->vtotal;
as_sdp->target_rr = 0; as_sdp->target_rr = 0;
} }

4
drivers/gpu/drm/i915/display/intel_dp_mst.c
View file

@ -341,6 +341,10 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
break; break;
} }
/* Allow using zero step to indicate one try */
if (!step)
break;
} }
if (slots < 0) { if (slots < 0) {

15
drivers/gpu/drm/i915/display/intel_hdcp.c
View file

@ -41,7 +41,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder,
u32 rekey_bit = 0; u32 rekey_bit = 0;
/* Here we assume HDMI is in TMDS mode of operation */ /* Here we assume HDMI is in TMDS mode of operation */
if (encoder->type != INTEL_OUTPUT_HDMI) if (!intel_encoder_is_hdmi(encoder))
return; return;
if (DISPLAY_VER(display) >= 30) { if (DISPLAY_VER(display) >= 30) {
@ -2188,6 +2188,19 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
drm_dbg_kms(display->drm, drm_dbg_kms(display->drm,
"HDCP2.2 Downstream topology change\n"); "HDCP2.2 Downstream topology change\n");
ret = hdcp2_authenticate_repeater_topology(connector);
if (!ret) {
intel_hdcp_update_value(connector,
DRM_MODE_CONTENT_PROTECTION_ENABLED,
true);
goto out;
}
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n",
connector->base.base.id, connector->base.name,
ret);
} else { } else {
drm_dbg_kms(display->drm, drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n",

4
drivers/gpu/drm/i915/display/skl_universal_plane.c
View file

@ -106,8 +106,6 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_Y216, DRM_FORMAT_Y216,
DRM_FORMAT_XYUV8888, DRM_FORMAT_XYUV8888,
DRM_FORMAT_XVYU2101010, DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
}; };
static const u32 icl_sdr_uv_plane_formats[] = { static const u32 icl_sdr_uv_plane_formats[] = {
@ -134,8 +132,6 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_Y216, DRM_FORMAT_Y216,
DRM_FORMAT_XYUV8888, DRM_FORMAT_XYUV8888,
DRM_FORMAT_XVYU2101010, DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
}; };
static const u32 icl_hdr_plane_formats[] = { static const u32 icl_hdr_plane_formats[] = {

6
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
View file

@ -209,8 +209,6 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
struct address_space *mapping = obj->base.filp->f_mapping; struct address_space *mapping = obj->base.filp->f_mapping;
unsigned int max_segment = i915_sg_segment_size(i915->drm.dev); unsigned int max_segment = i915_sg_segment_size(i915->drm.dev);
struct sg_table *st; struct sg_table *st;
struct sgt_iter sgt_iter;
struct page *page;
int ret; int ret;
/* /*
@ -239,9 +237,7 @@ rebuild_st:
* for PAGE_SIZE chunks instead may be helpful. * for PAGE_SIZE chunks instead may be helpful.
*/ */
if (max_segment > PAGE_SIZE) { if (max_segment > PAGE_SIZE) {
for_each_sgt_page(page, sgt_iter, st) shmem_sg_free_table(st, mapping, false, false);
put_page(page);
sg_free_table(st);
kfree(st); kfree(st);
max_segment = PAGE_SIZE; max_segment = PAGE_SIZE;

36
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
View file

@ -1469,6 +1469,19 @@ static void __reset_guc_busyness_stats(struct intel_guc *guc)
spin_unlock_irqrestore(&guc->timestamp.lock, flags); spin_unlock_irqrestore(&guc->timestamp.lock, flags);
} }
static void __update_guc_busyness_running_state(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned long flags;
spin_lock_irqsave(&guc->timestamp.lock, flags);
for_each_engine(engine, gt, id)
engine->stats.guc.running = false;
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
}
static void __update_guc_busyness_stats(struct intel_guc *guc) static void __update_guc_busyness_stats(struct intel_guc *guc)
{ {
struct intel_gt *gt = guc_to_gt(guc); struct intel_gt *gt = guc_to_gt(guc);
@ -1619,6 +1632,9 @@ void intel_guc_busyness_park(struct intel_gt *gt)
if (!guc_submission_initialized(guc)) if (!guc_submission_initialized(guc))
return; return;
/* Assume no engines are running and set running state to false */
__update_guc_busyness_running_state(guc);
/* /*
* There is a race with suspend flow where the worker runs after suspend * There is a race with suspend flow where the worker runs after suspend
* and causes an unclaimed register access warning. Cancel the worker * and causes an unclaimed register access warning. Cancel the worker
@ -5519,12 +5535,20 @@ static inline void guc_log_context(struct drm_printer *p,
{ {
drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id); drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca); drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", if (intel_context_pin_if_active(ce)) {
ce->ring->head, drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
ce->lrc_reg_state[CTX_RING_HEAD]); ce->ring->head,
drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", ce->lrc_reg_state[CTX_RING_HEAD]);
ce->ring->tail, drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
ce->lrc_reg_state[CTX_RING_TAIL]); ce->ring->tail,
ce->lrc_reg_state[CTX_RING_TAIL]);
intel_context_unpin(ce);
} else {
drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n",
ce->ring->head);
drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n",
ce->ring->tail);
}
drm_printf(p, "\t\tContext Pin Count: %u\n", drm_printf(p, "\t\tContext Pin Count: %u\n",
atomic_read(&ce->pin_count)); atomic_read(&ce->pin_count));
drm_printf(p, "\t\tGuC ID Ref Count: %u\n", drm_printf(p, "\t\tGuC ID Ref Count: %u\n",

6
drivers/gpu/drm/xe/regs/xe_oa_regs.h
View file

@ -51,6 +51,10 @@
/* Common to all OA units */ /* Common to all OA units */
#define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9) #define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9)
#define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8) #define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
#define OAG_OACONTROL_USED_BITS \
(OAG_OACONTROL_OA_PES_DISAG_EN | OAG_OACONTROL_OA_CCS_SELECT_MASK | \
OAG_OACONTROL_OA_COUNTER_SEL_MASK | OAG_OACONTROL_OA_COUNTER_ENABLE | \
OA_OACONTROL_REPORT_BC_MASK | OA_OACONTROL_COUNTER_SIZE_MASK)
#define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED) #define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
#define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14) #define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14)
@ -78,6 +82,8 @@
#define OAM_CONTEXT_CONTROL_OFFSET (0x1bc) #define OAM_CONTEXT_CONTROL_OFFSET (0x1bc)
#define OAM_CONTROL_OFFSET (0x194) #define OAM_CONTROL_OFFSET (0x194)
#define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1) #define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
#define OAM_OACONTROL_USED_BITS \
(OAM_CONTROL_COUNTER_SEL_MASK | OAG_OACONTROL_OA_COUNTER_ENABLE)
#define OAM_DEBUG_OFFSET (0x198) #define OAM_DEBUG_OFFSET (0x198)
#define OAM_STATUS_OFFSET (0x19c) #define OAM_STATUS_OFFSET (0x19c)
#define OAM_MMIO_TRG_OFFSET (0x1d0) #define OAM_MMIO_TRG_OFFSET (0x1d0)

42
drivers/gpu/drm/xe/xe_devcoredump.c
View file

@ -119,11 +119,7 @@ static ssize_t __xe_devcoredump_read(char *buffer, size_t count,
drm_puts(&p, "\n**** GuC CT ****\n"); drm_puts(&p, "\n**** GuC CT ****\n");
xe_guc_ct_snapshot_print(ss->guc.ct, &p); xe_guc_ct_snapshot_print(ss->guc.ct, &p);
/* drm_puts(&p, "\n**** Contexts ****\n");
* Don't add a new section header here because the mesa debug decoder
* tool expects the context information to be in the 'GuC CT' section.
*/
/* drm_puts(&p, "\n**** Contexts ****\n"); */
xe_guc_exec_queue_snapshot_print(ss->ge, &p); xe_guc_exec_queue_snapshot_print(ss->ge, &p);
drm_puts(&p, "\n**** Job ****\n"); drm_puts(&p, "\n**** Job ****\n");
@ -395,42 +391,34 @@ int xe_devcoredump_init(struct xe_device *xe)
/** /**
* xe_print_blob_ascii85 - print a BLOB to some useful location in ASCII85 * xe_print_blob_ascii85 - print a BLOB to some useful location in ASCII85
* *
* The output is split to multiple lines because some print targets, e.g. dmesg * The output is split into multiple calls to drm_puts() because some print
* cannot handle arbitrarily long lines. Note also that printing to dmesg in * targets, e.g. dmesg, cannot handle arbitrarily long lines. These targets may
* piece-meal fashion is not possible, each separate call to drm_puts() has a * add newlines, as is the case with dmesg: each drm_puts() call creates a
* line-feed automatically added! Therefore, the entire output line must be * separate line.
* constructed in a local buffer first, then printed in one atomic output call.
* *
* There is also a scheduler yield call to prevent the 'task has been stuck for * There is also a scheduler yield call to prevent the 'task has been stuck for
* 120s' kernel hang check feature from firing when printing to a slow target * 120s' kernel hang check feature from firing when printing to a slow target
* such as dmesg over a serial port. * such as dmesg over a serial port.
* *
* TODO: Add compression prior to the ASCII85 encoding to shrink huge buffers down.
*
* @p: the printer object to output to * @p: the printer object to output to
* @prefix: optional prefix to add to output string * @prefix: optional prefix to add to output string
* @suffix: optional suffix to add at the end. 0 disables it and is
* not added to the output, which is useful when using multiple calls
* to dump data to @p
* @blob: the Binary Large OBject to dump out * @blob: the Binary Large OBject to dump out
* @offset: offset in bytes to skip from the front of the BLOB, must be a multiple of sizeof(u32) * @offset: offset in bytes to skip from the front of the BLOB, must be a multiple of sizeof(u32)
* @size: the size in bytes of the BLOB, must be a multiple of sizeof(u32) * @size: the size in bytes of the BLOB, must be a multiple of sizeof(u32)
*/ */
void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, char suffix,
const void *blob, size_t offset, size_t size) const void *blob, size_t offset, size_t size)
{ {
const u32 *blob32 = (const u32 *)blob; const u32 *blob32 = (const u32 *)blob;
char buff[ASCII85_BUFSZ], *line_buff; char buff[ASCII85_BUFSZ], *line_buff;
size_t line_pos = 0; size_t line_pos = 0;
/*
* Splitting blobs across multiple lines is not compatible with the mesa
* debug decoder tool. Note that even dropping the explicit '\n' below
* doesn't help because the GuC log is so big some underlying implementation
* still splits the lines at 512K characters. So just bail completely for
* the moment.
*/
return;
#define DMESG_MAX_LINE_LEN 800 #define DMESG_MAX_LINE_LEN 800
#define MIN_SPACE (ASCII85_BUFSZ + 2) /* 85 + "\n\0" */ /* Always leave space for the suffix char and the \0 */
#define MIN_SPACE (ASCII85_BUFSZ + 2) /* 85 + "<suffix>\0" */
if (size & 3) if (size & 3)
drm_printf(p, "Size not word aligned: %zu", size); drm_printf(p, "Size not word aligned: %zu", size);
@ -462,7 +450,6 @@ void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix,
line_pos += strlen(line_buff + line_pos); line_pos += strlen(line_buff + line_pos);
if ((line_pos + MIN_SPACE) >= DMESG_MAX_LINE_LEN) { if ((line_pos + MIN_SPACE) >= DMESG_MAX_LINE_LEN) {
line_buff[line_pos++] = '\n';
line_buff[line_pos++] = 0; line_buff[line_pos++] = 0;
drm_puts(p, line_buff); drm_puts(p, line_buff);
@ -474,10 +461,11 @@ void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix,
} }
} }
if (line_pos) { if (suffix)
line_buff[line_pos++] = '\n'; line_buff[line_pos++] = suffix;
line_buff[line_pos++] = 0;
if (line_pos) {
line_buff[line_pos++] = 0;
drm_puts(p, line_buff); drm_puts(p, line_buff);
} }

2
drivers/gpu/drm/xe/xe_devcoredump.h
View file

@ -29,7 +29,7 @@ static inline int xe_devcoredump_init(struct xe_device *xe)
} }
#endif #endif
void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, char suffix,
const void *blob, size_t offset, size_t size); const void *blob, size_t offset, size_t size);
#endif #endif

4
drivers/gpu/drm/xe/xe_gt.c
View file

@ -532,8 +532,10 @@ static int all_fw_domain_init(struct xe_gt *gt)
if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt))
xe_lmtt_init_hw(&gt_to_tile(gt)->sriov.pf.lmtt); xe_lmtt_init_hw(&gt_to_tile(gt)->sriov.pf.lmtt);
if (IS_SRIOV_PF(gt_to_xe(gt))) if (IS_SRIOV_PF(gt_to_xe(gt))) {
xe_gt_sriov_pf_init(gt);
xe_gt_sriov_pf_init_hw(gt); xe_gt_sriov_pf_init_hw(gt);
}
xe_force_wake_put(gt_to_fw(gt), fw_ref); xe_force_wake_put(gt_to_fw(gt), fw_ref);

14
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
View file

@ -68,6 +68,19 @@ int xe_gt_sriov_pf_init_early(struct xe_gt *gt)
return 0; return 0;
} }
/**
* xe_gt_sriov_pf_init - Prepare SR-IOV PF data structures on PF.
* @gt: the &xe_gt to initialize
*
* Late one-time initialization of the PF data.
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_gt_sriov_pf_init(struct xe_gt *gt)
{
return xe_gt_sriov_pf_migration_init(gt);
}
static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe) static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe)
{ {
return GRAPHICS_VERx100(xe) == 1200; return GRAPHICS_VERx100(xe) == 1200;
@ -90,7 +103,6 @@ void xe_gt_sriov_pf_init_hw(struct xe_gt *gt)
pf_enable_ggtt_guest_update(gt); pf_enable_ggtt_guest_update(gt);
xe_gt_sriov_pf_service_update(gt); xe_gt_sriov_pf_service_update(gt);
xe_gt_sriov_pf_migration_init(gt);
} }
static u32 pf_get_vf_regs_stride(struct xe_device *xe) static u32 pf_get_vf_regs_stride(struct xe_device *xe)

6
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
View file

@ -10,6 +10,7 @@ struct xe_gt;
#ifdef CONFIG_PCI_IOV #ifdef CONFIG_PCI_IOV
int xe_gt_sriov_pf_init_early(struct xe_gt *gt); int xe_gt_sriov_pf_init_early(struct xe_gt *gt);
int xe_gt_sriov_pf_init(struct xe_gt *gt);
void xe_gt_sriov_pf_init_hw(struct xe_gt *gt); void xe_gt_sriov_pf_init_hw(struct xe_gt *gt);
void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid); void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid);
void xe_gt_sriov_pf_restart(struct xe_gt *gt); void xe_gt_sriov_pf_restart(struct xe_gt *gt);
@ -19,6 +20,11 @@ static inline int xe_gt_sriov_pf_init_early(struct xe_gt *gt)
return 0; return 0;
} }
static inline int xe_gt_sriov_pf_init(struct xe_gt *gt)
{
return 0;
}
static inline void xe_gt_sriov_pf_init_hw(struct xe_gt *gt) static inline void xe_gt_sriov_pf_init_hw(struct xe_gt *gt)
{ {
} }

3
drivers/gpu/drm/xe/xe_guc_ct.c
View file

@ -1724,7 +1724,8 @@ void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot,
snapshot->g2h_outstanding); snapshot->g2h_outstanding);
if (snapshot->ctb) if (snapshot->ctb)
xe_print_blob_ascii85(p, "CTB data", snapshot->ctb, 0, snapshot->ctb_size); xe_print_blob_ascii85(p, "CTB data", '\n',
snapshot->ctb, 0, snapshot->ctb_size);
} else { } else {
drm_puts(p, "CT disabled\n"); drm_puts(p, "CT disabled\n");
} }

4
drivers/gpu/drm/xe/xe_guc_log.c
View file

@ -211,8 +211,10 @@ void xe_guc_log_snapshot_print(struct xe_guc_log_snapshot *snapshot, struct drm_
remain = snapshot->size; remain = snapshot->size;
for (i = 0; i < snapshot->num_chunks; i++) { for (i = 0; i < snapshot->num_chunks; i++) {
size_t size = min(GUC_LOG_CHUNK_SIZE, remain); size_t size = min(GUC_LOG_CHUNK_SIZE, remain);
const char *prefix = i ? NULL : "Log data";
char suffix = i == snapshot->num_chunks - 1 ? '\n' : 0;
xe_print_blob_ascii85(p, i ? NULL : "Log data", snapshot->copy[i], 0, size); xe_print_blob_ascii85(p, prefix, suffix, snapshot->copy[i], 0, size);
remain -= size; remain -= size;
} }
} }

21
drivers/gpu/drm/xe/xe_oa.c
View file

@ -237,7 +237,6 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
u32 tail, hw_tail, partial_report_size, available; u32 tail, hw_tail, partial_report_size, available;
int report_size = stream->oa_buffer.format->size; int report_size = stream->oa_buffer.format->size;
unsigned long flags; unsigned long flags;
bool pollin;
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
@ -282,11 +281,11 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream)
stream->oa_buffer.tail = tail; stream->oa_buffer.tail = tail;
available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head); available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
pollin = available >= stream->wait_num_reports * report_size; stream->pollin = available >= stream->wait_num_reports * report_size;
spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
return pollin; return stream->pollin;
} }
static enum hrtimer_restart xe_oa_poll_check_timer_cb(struct hrtimer *hrtimer) static enum hrtimer_restart xe_oa_poll_check_timer_cb(struct hrtimer *hrtimer)
@ -294,10 +293,8 @@ static enum hrtimer_restart xe_oa_poll_check_timer_cb(struct hrtimer *hrtimer)
struct xe_oa_stream *stream = struct xe_oa_stream *stream =
container_of(hrtimer, typeof(*stream), poll_check_timer); container_of(hrtimer, typeof(*stream), poll_check_timer);
if (xe_oa_buffer_check_unlocked(stream)) { if (xe_oa_buffer_check_unlocked(stream))
stream->pollin = true;
wake_up(&stream->poll_wq); wake_up(&stream->poll_wq);
}
hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period_ns)); hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period_ns));
@ -452,6 +449,12 @@ static u32 __oa_ccs_select(struct xe_oa_stream *stream)
return val; return val;
} }
static u32 __oactrl_used_bits(struct xe_oa_stream *stream)
{
return stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG ?
OAG_OACONTROL_USED_BITS : OAM_OACONTROL_USED_BITS;
}
static void xe_oa_enable(struct xe_oa_stream *stream) static void xe_oa_enable(struct xe_oa_stream *stream)
{ {
const struct xe_oa_format *format = stream->oa_buffer.format; const struct xe_oa_format *format = stream->oa_buffer.format;
@ -472,14 +475,14 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG) stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG)
val |= OAG_OACONTROL_OA_PES_DISAG_EN; val |= OAG_OACONTROL_OA_PES_DISAG_EN;
xe_mmio_write32(&stream->gt->mmio, regs->oa_ctrl, val); xe_mmio_rmw32(&stream->gt->mmio, regs->oa_ctrl, __oactrl_used_bits(stream), val);
} }
static void xe_oa_disable(struct xe_oa_stream *stream) static void xe_oa_disable(struct xe_oa_stream *stream)
{ {
struct xe_mmio *mmio = &stream->gt->mmio; struct xe_mmio *mmio = &stream->gt->mmio;
xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctrl, 0); xe_mmio_rmw32(mmio, __oa_regs(stream)->oa_ctrl, __oactrl_used_bits(stream), 0);
if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl, if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl,
OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50000, NULL, false)) OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50000, NULL, false))
drm_err(&stream->oa->xe->drm, drm_err(&stream->oa->xe->drm,
@ -2534,6 +2537,8 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
u->type = DRM_XE_OA_UNIT_TYPE_OAM; u->type = DRM_XE_OA_UNIT_TYPE_OAM;
} }
xe_mmio_write32(&gt->mmio, u->regs.oa_ctrl, 0);
/* Ensure MMIO trigger remains disabled till there is a stream */ /* Ensure MMIO trigger remains disabled till there is a stream */
xe_mmio_write32(&gt->mmio, u->regs.oa_debug, xe_mmio_write32(&gt->mmio, u->regs.oa_debug,
oag_configure_mmio_trigger(NULL, false)); oag_configure_mmio_trigger(NULL, false));

1
include/drm/drm_print.h
View file

@ -32,6 +32,7 @@
#include <linux/dynamic_debug.h> #include <linux/dynamic_debug.h>
#include <drm/drm.h> #include <drm/drm.h>
#include <drm/drm_device.h>
struct debugfs_regset32; struct debugfs_regset32;
struct drm_device; struct drm_device;

9
include/uapi/drm/amdgpu_drm.h
View file

@ -411,13 +411,20 @@ struct drm_amdgpu_gem_userptr {
/* GFX12 and later: */ /* GFX12 and later: */
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
/* These are DCC recompression setting for memory management: */ /* These are DCC recompression settings for memory management: */
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
* to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
/* bit gap */
#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
/* Set/Get helpers for tiling flags. */ /* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \ #define AMDGPU_TILING_SET(field, value) \